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target/mips: Fix WatchHi.M handling

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bit 31 (M) of WatchHiN register is a read-only register indicating
whether the next WatchHi register is present. It must not be reset
during user writes to the register.

Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: David Daney <david.daney@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@fungible.com>
Message-Id: <20220511212953.74738-1-philmd@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Marcin Nowakowski 2021-05-26 11:35:06 +02:00 committed by Philippe Mathieu-Daudé
parent 30796f5567
commit a6bc80f7b1
3 changed files with 4 additions and 2 deletions
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2
target/mips/cpu.c
View File

@ -305,7 +305,7 @@ static void mips_cpu_reset(DeviceState *dev)
for (i = 0; i < 7; i++) {
env->CP0_WatchLo[i] = 0;
env->CP0_WatchHi[i] = 0x80000000;
env->CP0_WatchHi[i] = 1 << CP0WH_M;
}
env->CP0_WatchLo[7] = 0;
env->CP0_WatchHi[7] = 0;

1
target/mips/cpu.h
View File

@ -1005,6 +1005,7 @@ typedef struct CPUArchState {
*/
uint64_t CP0_WatchHi[8];
#define CP0WH_ASID 16
#define CP0WH_M 31
/*
* CP0 Register 20
*/

3
target/mips/tcg/sysemu/cp0_helper.c
View File

@ -1396,10 +1396,11 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */
if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
mask |= 0xFFFFFFFF00000000ULL; /* MMID */
}
env->CP0_WatchHi[sel] = arg1 & mask;
env->CP0_WatchHi[sel] = m_bit | (arg1 & mask);
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
}