From a722701dd364b82dc115e94a29d767949f796000 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Wed, 19 May 2021 23:57:38 +0800 Subject: [PATCH] target/riscv: Dump CSR mscratch/sscratch/satp This dumps the CSR mscratch/sscratch/satp and meanwhile aligns the output of CSR mtval/stval. Signed-off-by: Changbin Du Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20210519155738.20486-1-changbin.du@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index aa48bca830..ee2523f66b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -286,12 +286,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); } + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); #endif for (i = 0; i < 32; i++) {