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target/ppc: Implement large decrementer support for TCG
Prior to POWER9 the decrementer was a 32-bit register which decremented with each tick of the timebase. From POWER9 onwards the decrementer can be set to operate in a mode called large decrementer where it acts as a n-bit decrementing register which is visible as a 64-bit register, that is the value of the decrementer is sign extended to 64 bits (where n is implementation dependant). The mode in which the decrementer operates is controlled by the LPCR_LD bit in the logical paritition control register (LPCR). >From POWER9 onwards the HDEC (hypervisor decrementer) was enlarged to h-bits, also sign extended to 64 bits (where h is implementation dependant). Note this isn't configurable and is always enabled. On POWER9 the large decrementer and hdec are both 56 bits, as represented by the lrg_decr_bits cpu class property. Since they are the same size we only add one property for now, which could be extended in the case they ever differ in the future. We also add the lrg_decr_bits property for POWER5+/7/8 since it is used to determine the size of the hdec, which is only generated on the POWER5+ processor and later. On these processors it is 32 bits. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190301024317.22137-2-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Suraj Jitindar Singh
David Gibson
parent
c982f5cf9a
commit
a8dafa5251
90
hw/ppc/ppc.c
90
hw/ppc/ppc.c
@ -744,11 +744,10 @@ bool ppc_decr_clear_on_delivery(CPUPPCState *env)
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return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED);
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}
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static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
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static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint32_t decr;
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int64_t diff;
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int64_t decr, diff;
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diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if (diff >= 0) {
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@ -758,27 +757,49 @@ static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
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} else {
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decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
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}
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LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
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LOG_TB("%s: %016" PRIx64 "\n", __func__, decr);
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return decr;
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}
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uint32_t cpu_ppc_load_decr (CPUPPCState *env)
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target_ulong cpu_ppc_load_decr(CPUPPCState *env)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t decr;
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if (kvm_enabled()) {
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return env->spr[SPR_DECR];
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}
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return _cpu_ppc_load_decr(env, tb_env->decr_next);
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decr = _cpu_ppc_load_decr(env, tb_env->decr_next);
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/*
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* If large decrementer is enabled then the decrementer is signed extened
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* to 64 bits, otherwise it is a 32 bit value.
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*/
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if (env->spr[SPR_LPCR] & LPCR_LD) {
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return decr;
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}
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return (uint32_t) decr;
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}
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uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)
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target_ulong cpu_ppc_load_hdecr(CPUPPCState *env)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t hdecr;
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return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
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hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next);
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/*
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* If we have a large decrementer (POWER9 or later) then hdecr is sign
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* extended to 64 bits, otherwise it is 32 bits.
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*/
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if (pcc->lrg_decr_bits > 32) {
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return hdecr;
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}
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return (uint32_t) hdecr;
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}
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uint64_t cpu_ppc_load_purr (CPUPPCState *env)
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@ -832,13 +853,22 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
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QEMUTimer *timer,
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void (*raise_excp)(void *),
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void (*lower_excp)(PowerPCCPU *),
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uint32_t decr, uint32_t value)
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target_ulong decr, target_ulong value,
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int nr_bits)
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{
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CPUPPCState *env = &cpu->env;
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t now, next;
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bool negative;
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LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
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/* Truncate value to decr_width and sign extend for simplicity */
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value &= ((1ULL << nr_bits) - 1);
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negative = !!(value & (1ULL << (nr_bits - 1)));
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if (negative) {
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value |= (0xFFFFFFFFULL << nr_bits);
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}
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LOG_TB("%s: " TARGET_FMT_lx " => " TARGET_FMT_lx "\n", __func__,
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decr, value);
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if (kvm_enabled()) {
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@ -860,15 +890,15 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
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* an edge interrupt, so raise it here too.
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*/
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if ((value < 3) ||
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((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && (value & 0x80000000)) ||
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((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && (value & 0x80000000)
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&& !(decr & 0x80000000))) {
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((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && negative) ||
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((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && negative
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&& !(decr & (1ULL << (nr_bits - 1))))) {
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(*raise_excp)(cpu);
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return;
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}
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/* On MSB level based systems a 0 for the MSB stops interrupt delivery */
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if (!(value & 0x80000000) && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) {
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if (!negative && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) {
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(*lower_excp)(cpu);
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}
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@ -881,21 +911,27 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
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timer_mod(timer, next);
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}
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static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr,
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uint32_t value)
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static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr,
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target_ulong value, int nr_bits)
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{
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ppc_tb_t *tb_env = cpu->env.tb_env;
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__cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
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tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr,
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value);
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value, nr_bits);
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}
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void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)
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void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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int nr_bits = 32;
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_cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value);
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if (env->spr[SPR_LPCR] & LPCR_LD) {
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nr_bits = pcc->lrg_decr_bits;
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}
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_cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits);
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}
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static void cpu_ppc_decr_cb(void *opaque)
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@ -905,23 +941,25 @@ static void cpu_ppc_decr_cb(void *opaque)
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cpu_ppc_decr_excp(cpu);
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}
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static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr,
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uint32_t value)
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static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr,
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target_ulong value, int nr_bits)
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{
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ppc_tb_t *tb_env = cpu->env.tb_env;
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if (tb_env->hdecr_timer != NULL) {
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__cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
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tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower,
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hdecr, value);
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hdecr, value, nr_bits);
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}
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}
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void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)
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void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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_cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value);
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_cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value,
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pcc->lrg_decr_bits);
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}
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static void cpu_ppc_hdecr_cb(void *opaque)
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@ -951,8 +989,8 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
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* if a decrementer exception is pending when it enables msr_ee at startup,
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* it's not ready to handle it...
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*/
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_cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF);
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_cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF);
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_cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32);
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_cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32);
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cpu_ppc_store_purr(cpu, 0x0000000000000000ULL);
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}
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@ -558,6 +558,14 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
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pcc->radix_page_info->count *
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sizeof(radix_AP_encodings[0]))));
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}
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/*
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* We set this property to let the guest know that it can use the large
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* decrementer and its width in bits.
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*/
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if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
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_FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
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pcc->lrg_decr_bits)));
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}
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static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
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@ -393,9 +393,38 @@ static void cap_nested_kvm_hv_apply(sPAPRMachineState *spapr,
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static void cap_large_decr_apply(sPAPRMachineState *spapr,
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uint8_t val, Error **errp)
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{
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if (val)
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PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
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if (!val) {
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return; /* Disabled by default */
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}
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if (tcg_enabled()) {
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if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
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spapr->max_compat_pvr)) {
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error_setg(errp,
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"Large decrementer only supported on POWER9, try -cpu POWER9");
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return;
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}
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} else {
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error_setg(errp,
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"No large decrementer support, try cap-large-decr=off");
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}
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}
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static void cap_large_decr_cpu_apply(sPAPRMachineState *spapr,
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PowerPCCPU *cpu,
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uint8_t val, Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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target_ulong lpcr = env->spr[SPR_LPCR];
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if (val) {
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lpcr |= LPCR_LD;
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} else {
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lpcr &= ~LPCR_LD;
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}
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ppc_store_lpcr(cpu, lpcr);
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}
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sPAPRCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
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@ -484,6 +513,7 @@ sPAPRCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
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.set = spapr_cap_set_bool,
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.type = "bool",
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.apply = cap_large_decr_apply,
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.cpu_apply = cap_large_decr_cpu_apply,
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},
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};
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@ -190,6 +190,7 @@ typedef struct PowerPCCPUClass {
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#endif
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const PPCHash64Options *hash64_opts;
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struct ppc_radix_page_info *radix_page_info;
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uint32_t lrg_decr_bits;
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void (*init_proc)(CPUPPCState *env);
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int (*check_pow)(CPUPPCState *env);
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int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
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@ -1321,10 +1321,10 @@ uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
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void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
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void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
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bool ppc_decr_clear_on_delivery(CPUPPCState *env);
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uint32_t cpu_ppc_load_decr (CPUPPCState *env);
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void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
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uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
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void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
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target_ulong cpu_ppc_load_decr(CPUPPCState *env);
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void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
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target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
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void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
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uint64_t cpu_ppc_load_purr (CPUPPCState *env);
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uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
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uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
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@ -1109,7 +1109,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
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case POWERPC_MMU_3_00: /* P9 */
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lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
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(LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
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LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR |
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LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
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(LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
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LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
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LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
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@ -7417,7 +7417,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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#if !defined(NO_TIMER_DUMP)
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cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
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#if !defined(CONFIG_USER_ONLY)
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" DECR %08" PRIu32
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" DECR " TARGET_FMT_lu
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#endif
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"\n",
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cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
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@ -8376,6 +8376,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
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#if defined(CONFIG_SOFTMMU)
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pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
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pcc->hash64_opts = &ppc_hash64_opts_basic;
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pcc->lrg_decr_bits = 32;
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#endif
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pcc->excp_model = POWERPC_EXCP_970;
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pcc->bus_model = PPC_FLAGS_INPUT_970;
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@ -8550,6 +8551,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
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#if defined(CONFIG_SOFTMMU)
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pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
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pcc->hash64_opts = &ppc_hash64_opts_POWER7;
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pcc->lrg_decr_bits = 32;
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#endif
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pcc->excp_model = POWERPC_EXCP_POWER7;
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pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
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@ -8718,6 +8720,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
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#if defined(CONFIG_SOFTMMU)
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pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
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pcc->hash64_opts = &ppc_hash64_opts_POWER7;
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pcc->lrg_decr_bits = 32;
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#endif
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pcc->excp_model = POWERPC_EXCP_POWER8;
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pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
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@ -8926,6 +8929,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
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/* segment page size remain the same */
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pcc->hash64_opts = &ppc_hash64_opts_POWER7;
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pcc->radix_page_info = &POWER9_radix_page_info;
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pcc->lrg_decr_bits = 56;
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#endif
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pcc->excp_model = POWERPC_EXCP_POWER9;
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pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
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