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Misc patches queue

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Build fixes:
 - Only define OS_OBJECT_USE_OBJC with gcc
 
 Overall cleanups:
 - Do not declare function prototypes using 'extern' keyword
 - Remove unmaintained HAX accelerator
 - Have FEWatchFunc handlers return G_SOURCE_CONTINUE/REMOVE instead of boolean
 - Avoid modifying QOM class internals from instance in pmbus_device
 - Avoid variable-length array in xhci_get_port_bandwidth
 - Remove unuseful kvmclock_create() stub
 - Style: permit inline loop variables
 - Various header cleanups
 - Various spelling fixes
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmTw0oUACgkQ4+MsLN6t
 wN7nZQ/+Jyrw1TnHiKV8nS5NKtQIszMTcAbrcuV8YCk0XgwprmrLzxOsOcVOU+MN
 C9SHOhGGcu8NKho73CDrsKqye/IKm8rumMm0hcZrtqGS+3MX9RQzDBUgRgihgD9b
 78Pmiz/91mrsV4zjXBkWLILipjDUwAL0oXh+MLfkmkTdzJMVfllF5KfF+hdOipwq
 +ECOzwEAFUtCWQk51aLGfrg9SarKC2jtRBEvd1RhwfvXAMCdGP9+pfXJQqkT7ZTK
 Hf4TuOHkzZjHumHGGcJn+P1WHM6W3ILdocG7AAl+/0Jwkx4vhR+6MENJGLxqg4pa
 VTnOpJiL/HsY8319mTswTmlxqmotEDakGjdaRm4ClWPxPksF7zQkdTspBx0/Qayu
 SPr7U5gFLPXMhCpMnrznvjCS+C/dqLYrJAczs9Ecv6KawOIwMiPRzc0SyimCV4DI
 kcpL88Vn4unoBCF7AdiDluPoY2Q41TZ6gRa7B1/nI/4j9Y+Gs/gWQxYHjMlDso+O
 sNgMJ+sqIPW9n1vhl9s6AQweBYnMRW34A5iok9MV0HyFTxNKMoCoR8Ssfk9YzT+L
 mK5a9AfgT8FrhtQXQz6ojIPFM8Q4zGcAQOMudpPiDICDAJaPuUpzL3XVwStT6Rfc
 YL0+Nb+Ja5hPh0fAhgX3BH0EsqruW+DA8rEZfIgAIXDbOC5QFIo=
 =SVsZ
 -----END PGP SIGNATURE-----

Merge tag 'misc-20230831' of https://github.com/philmd/qemu into staging

Misc patches queue

Build fixes:
- Only define OS_OBJECT_USE_OBJC with gcc

Overall cleanups:
- Do not declare function prototypes using 'extern' keyword
- Remove unmaintained HAX accelerator
- Have FEWatchFunc handlers return G_SOURCE_CONTINUE/REMOVE instead of boolean
- Avoid modifying QOM class internals from instance in pmbus_device
- Avoid variable-length array in xhci_get_port_bandwidth
- Remove unuseful kvmclock_create() stub
- Style: permit inline loop variables
- Various header cleanups
- Various spelling fixes

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmTw0oUACgkQ4+MsLN6t
# wN7nZQ/+Jyrw1TnHiKV8nS5NKtQIszMTcAbrcuV8YCk0XgwprmrLzxOsOcVOU+MN
# C9SHOhGGcu8NKho73CDrsKqye/IKm8rumMm0hcZrtqGS+3MX9RQzDBUgRgihgD9b
# 78Pmiz/91mrsV4zjXBkWLILipjDUwAL0oXh+MLfkmkTdzJMVfllF5KfF+hdOipwq
# +ECOzwEAFUtCWQk51aLGfrg9SarKC2jtRBEvd1RhwfvXAMCdGP9+pfXJQqkT7ZTK
# Hf4TuOHkzZjHumHGGcJn+P1WHM6W3ILdocG7AAl+/0Jwkx4vhR+6MENJGLxqg4pa
# VTnOpJiL/HsY8319mTswTmlxqmotEDakGjdaRm4ClWPxPksF7zQkdTspBx0/Qayu
# SPr7U5gFLPXMhCpMnrznvjCS+C/dqLYrJAczs9Ecv6KawOIwMiPRzc0SyimCV4DI
# kcpL88Vn4unoBCF7AdiDluPoY2Q41TZ6gRa7B1/nI/4j9Y+Gs/gWQxYHjMlDso+O
# sNgMJ+sqIPW9n1vhl9s6AQweBYnMRW34A5iok9MV0HyFTxNKMoCoR8Ssfk9YzT+L
# mK5a9AfgT8FrhtQXQz6ojIPFM8Q4zGcAQOMudpPiDICDAJaPuUpzL3XVwStT6Rfc
# YL0+Nb+Ja5hPh0fAhgX3BH0EsqruW+DA8rEZfIgAIXDbOC5QFIo=
# =SVsZ
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 31 Aug 2023 13:48:53 EDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'misc-20230831' of https://github.com/philmd/qemu: (39 commits)
  build: Only define OS_OBJECT_USE_OBJC with gcc
  tests/tcg/aarch64: Rename bti-crt.inc.c -> bti-crt.c.inc
  ui: spelling fixes
  util: spelling fixes
  util/fifo8: Fix typo in fifo8_push_all() description
  hw/i386: Rename 'hw/kvm/clock.h' -> 'hw/i386/kvm/clock.h'
  hw/i386: Remove unuseful kvmclock_create() stub
  hw/usb/hcd-xhci: Avoid variable-length array in xhci_get_port_bandwidth()
  hw/usb: spelling fixes
  hw/sd: spelling fixes
  hw/mips: spelling fixes
  hw/display: spelling fixes
  hw/ide: spelling fixes
  hw/i2c: spelling fixes
  hw/i2c/pmbus_device: Fix modifying QOM class internals from instance
  hw/char/pl011: Replace magic values by register field definitions
  hw/char/pl011: Remove duplicated PL011_INT_[RT]X definitions
  hw/char/pl011: Display register name in trace events
  hw/char/pl011: Restrict MemoryRegionOps implementation access sizes
  hw/char: Have FEWatchFunc handlers return G_SOURCE_CONTINUE/REMOVE
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-09-05 09:21:42 -04:00
commit a9c17e9a21
186 changed files with 307 additions and 3441 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
MAINTAINERS
View File

@ -543,14 +543,6 @@ F: include/sysemu/xen.h
F: include/sysemu/xen-mapcache.h
F: stubs/xen-hw-stub.c
Guest CPU Cores (HAXM)
---------------------
X86 HAXM CPUs
S: Orphan
F: accel/stubs/hax-stub.c
F: include/sysemu/hax.h
F: target/i386/hax/
Guest CPU Cores (NVMM)
----------------------
NetBSD Virtual Machine Monitor (NVMM) CPU support

3
accel/Kconfig
View File

@ -4,9 +4,6 @@ config WHPX
config NVMM
bool
config HAX
bool
config HVF
bool

24
accel/stubs/hax-stub.c
View File

@ -1,24 +0,0 @@
/*
* QEMU HAXM support
*
* Copyright (c) 2015, Intel Corporation
*
* Copyright 2016 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* See the COPYING file in the top-level directory.
*
*/
#include "qemu/osdep.h"
#include "sysemu/hax.h"
bool hax_allowed;
int hax_sync_vcpus(void)
{
return 0;
}

1
accel/stubs/meson.build
View File

@ -1,5 +1,4 @@
sysemu_stubs_ss = ss.source_set()
sysemu_stubs_ss.add(when: 'CONFIG_HAX', if_false: files('hax-stub.c'))
sysemu_stubs_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c'))
sysemu_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
sysemu_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c'))

2
accel/tcg/tb-maint.c
View File

@ -1,5 +1,5 @@
/*
* Translation Block Maintaince
* Translation Block Maintenance
*
* Copyright (c) 2003 Fabrice Bellard
*

6
bsd-user/bsd-file.h
View File

@ -51,10 +51,8 @@ do { \
unlock_user(p1, arg1, 0); \
} while (0)
extern struct iovec *lock_iovec(int type, abi_ulong target_addr, int count,
int copy);
extern void unlock_iovec(struct iovec *vec, abi_ulong target_addr, int count,
int copy);
struct iovec *lock_iovec(int type, abi_ulong target_addr, int count, int copy);
void unlock_iovec(struct iovec *vec, abi_ulong target_addr, int count, int copy);
int safe_open(const char *path, int flags, mode_t mode);
int safe_openat(int fd, const char *path, int flags, mode_t mode);

2
contrib/plugins/cache.c
View File

@ -350,7 +350,7 @@ static int in_cache(Cache *cache, uint64_t addr)
* @cache: The cache under simulation
* @addr: The address of the requested memory location
*
* Returns true if the requsted data is hit in the cache and false when missed.
* Returns true if the requested data is hit in the cache and false when missed.
* The cache is updated on miss for the next access.
*/
static bool access_cache(Cache *cache, uint64_t addr)

2
contrib/plugins/lockstep.c
View File

@ -108,7 +108,7 @@ static void report_divergance(ExecState *us, ExecState *them)
/*
* If we have diverged before did we get back on track or are we
* totally loosing it?
* totally losing it?
*/
if (divergence_log) {
DivergeState *last = (DivergeState *) divergence_log->data;

13
crypto/hmacpriv.h
View File

@ -28,19 +28,18 @@ struct QCryptoHmacDriver {
void (*hmac_free)(QCryptoHmac *hmac);
};
extern void *qcrypto_hmac_ctx_new(QCryptoHashAlgorithm alg,
const uint8_t *key, size_t nkey,
Error **errp);
void *qcrypto_hmac_ctx_new(QCryptoHashAlgorithm alg,
const uint8_t *key, size_t nkey,
Error **errp);
extern QCryptoHmacDriver qcrypto_hmac_lib_driver;
#ifdef CONFIG_AF_ALG
#include "afalgpriv.h"
extern QCryptoAFAlg *
qcrypto_afalg_hmac_ctx_new(QCryptoHashAlgorithm alg,
const uint8_t *key, size_t nkey,
Error **errp);
QCryptoAFAlg *qcrypto_afalg_hmac_ctx_new(QCryptoHashAlgorithm alg,
const uint8_t *key, size_t nkey,
Error **errp);
extern QCryptoHmacDriver qcrypto_hmac_afalg_driver;
#endif

2
docs/about/build-platforms.rst
View File

@ -52,7 +52,7 @@ Those hosts are officially supported, with various accelerators:
* - SPARC
- tcg
* - x86
- hax, hvf (64 bit only), kvm, nvmm, tcg, whpx (64 bit only), xen
- hvf (64 bit only), kvm, nvmm, tcg, whpx (64 bit only), xen
Other host architectures are not supported. It is possible to build QEMU system
emulation on an unsupported host architecture using the configure

6
docs/about/deprecated.rst
View File

@ -105,12 +105,6 @@ Use ``-machine hpet=off`` instead.
The ``-no-acpi`` setting has been turned into a machine property.
Use ``-machine acpi=off`` instead.
``-accel hax`` (since 8.0)
''''''''''''''''''''''''''
The HAXM project has been retired (see https://github.com/intel/haxm#status).
Use "whpx" (on Windows) or "hvf" (on macOS) instead.
``-async-teardown`` (since 8.1)
'''''''''''''''''''''''''''''''

2
docs/about/index.rst
View File

@ -8,7 +8,7 @@ QEMU can be used in several different ways. The most common is for
:ref:`System Emulation`, where it provides a virtual model of an
entire machine (CPU, memory and emulated devices) to run a guest OS.
In this mode the CPU may be fully emulated, or it may work with a
hypervisor such as KVM, Xen, Hax or Hypervisor.Framework to allow the
hypervisor such as KVM, Xen or Hypervisor.Framework to allow the
guest to run directly on the host CPU.
The second supported way to use QEMU is :ref:`User Mode Emulation`,

11
docs/about/removed-features.rst
View File

@ -659,15 +659,18 @@ Use ``Icelake-Server`` instead.
System accelerators
-------------------
Userspace local APIC with KVM (x86, removed 8.0)
''''''''''''''''''''''''''''''''''''''''''''''''
Userspace local APIC with KVM (x86, removed in 8.0)
'''''''''''''''''''''''''''''''''''''''''''''''''''
``-M kernel-irqchip=off`` cannot be used on KVM if the CPU model includes
a local APIC. The ``split`` setting is supported, as is using ``-M
kernel-irqchip=off`` when the CPU does not have a local APIC.
System accelerators
-------------------
HAXM (``-accel hax``) (removed in 8.2)
''''''''''''''''''''''''''''''''''''''
The HAXM project has been retired (see https://github.com/intel/haxm#status).
Use "whpx" (on Windows) or "hvf" (on macOS) instead.
MIPS "Trap-and-Emulate" KVM support (removed in 8.0)
''''''''''''''''''''''''''''''''''''''''''''''''''''

2
docs/system/index.rst
View File

@ -6,7 +6,7 @@ System Emulation
This section of the manual is the overall guide for users using QEMU
for full system emulation (as opposed to user-mode emulation).
This includes working with hypervisors such as KVM, Xen, Hax
This includes working with hypervisors such as KVM, Xen
or Hypervisor.Framework.
.. toctree::

3
docs/system/introduction.rst
View File

@ -21,9 +21,6 @@ Tiny Code Generator (TCG) capable of emulating many CPUs.
* - Xen
- Linux (as dom0)
- Arm, x86
* - Intel HAXM (hax)
- Linux, Windows
- x86
* - Hypervisor Framework (hvf)
- MacOS
- x86 (64 bit only), Arm (64 bit only)

8
hw/char/cadence_uart.c
View File

@ -307,11 +307,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
/* instant drain the fifo when there's no back-end */
if (!qemu_chr_fe_backend_connected(&s->chr)) {
s->tx_count = 0;
return FALSE;
return G_SOURCE_REMOVE;
}
if (!s->tx_count) {
return FALSE;
return G_SOURCE_REMOVE;
}
ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
@ -326,12 +326,12 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
cadence_uart_xmit, s);
if (!r) {
s->tx_count = 0;
return FALSE;
return G_SOURCE_REMOVE;
}
}
uart_update_status(s);
return FALSE;
return G_SOURCE_REMOVE;
}
static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,

6
hw/char/cmsdk-apb-uart.c
View File

@ -199,7 +199,7 @@ static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque)
s->watch_tag = 0;
if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) {
return FALSE;
return G_SOURCE_REMOVE;
}
ret = qemu_chr_fe_write(&s->chr, &s->txbuf, 1);
@ -215,7 +215,7 @@ static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque)
}
/* Transmit pending */
trace_cmsdk_apb_uart_tx_pending();
return FALSE;
return G_SOURCE_REMOVE;
}
buffer_drained:
@ -227,7 +227,7 @@ buffer_drained:
s->intstatus |= R_INTSTATUS_TX_MASK;
}
cmsdk_apb_uart_update(s);
return FALSE;
return G_SOURCE_REMOVE;
}
static void uart_cancel_transmit(CMSDKAPBUART *s)

8
hw/char/ibex_uart.c
View File

@ -147,7 +147,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond,
/* instant drain the fifo when there's no back-end */
if (!qemu_chr_fe_backend_connected(&s->chr)) {
s->tx_level = 0;
return FALSE;
return G_SOURCE_REMOVE;
}
if (!s->tx_level) {
@ -156,7 +156,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond,
s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
ibex_uart_update_irqs(s);
return FALSE;
return G_SOURCE_REMOVE;
}
ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level);
@ -171,7 +171,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond,
ibex_uart_xmit, s);
if (!r) {
s->tx_level = 0;
return FALSE;
return G_SOURCE_REMOVE;
}
}
@ -192,7 +192,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond,
}
ibex_uart_update_irqs(s);
return FALSE;
return G_SOURCE_REMOVE;
}
static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,

4
hw/char/nrf51_uart.c
View File

@ -93,13 +93,13 @@ static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque)
*/
goto buffer_drained;
}
return FALSE;
return G_SOURCE_REMOVE;
}
buffer_drained:
s->reg[R_UART_TXDRDY] = 1;
s->pending_tx_byte = false;
return FALSE;
return G_SOURCE_REMOVE;
}
static void uart_cancel_transmit(NRF51UARTState *s)

58
hw/char/pl011.c
View File

@ -48,14 +48,15 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
return dev;
}
#define PL011_INT_TX 0x20
#define PL011_INT_RX 0x10
/* Flag Register, UARTFR */
#define PL011_FLAG_TXFE 0x80
#define PL011_FLAG_RXFF 0x40
#define PL011_FLAG_TXFF 0x20
#define PL011_FLAG_RXFE 0x10
/* Data Register, UARTDR */
#define DR_BE (1 << 10)
/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */
#define INT_OE (1 << 10)
#define INT_BE (1 << 9)
@ -71,11 +72,33 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
#define INT_E (INT_OE | INT_BE | INT_PE | INT_FE)
#define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS)
/* Line Control Register, UARTLCR_H */
#define LCR_FEN (1 << 4)
#define LCR_BRK (1 << 0)
static const unsigned char pl011_id_arm[8] =
{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
static const unsigned char pl011_id_luminary[8] =
{ 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
static const char *pl011_regname(hwaddr offset)
{
static const char *const rname[] = {
[0] = "DR", [1] = "RSR", [6] = "FR", [8] = "ILPR", [9] = "IBRD",
[10] = "FBRD", [11] = "LCRH", [12] = "CR", [13] = "IFLS", [14] = "IMSC",
[15] = "RIS", [16] = "MIS", [17] = "ICR", [18] = "DMACR",
};
unsigned idx = offset >> 2;
if (idx < ARRAY_SIZE(rname) && rname[idx]) {
return rname[idx];
}
if (idx >= 0x3f8 && idx <= 0x400) {
return "ID";
}
return "UNKN";
}
/* Which bits in the interrupt status matter for each outbound IRQ line ? */
static const uint32_t irqmask[] = {
INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */
@ -100,7 +123,7 @@ static void pl011_update(PL011State *s)
static bool pl011_is_fifo_enabled(PL011State *s)
{
return (s->lcr & 0x10) != 0;
return (s->lcr & LCR_FEN) != 0;
}
static inline unsigned pl011_get_fifo_depth(PL011State *s)
@ -138,7 +161,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
s->flags |= PL011_FLAG_RXFE;
}
if (s->read_count == s->read_trigger - 1)
s->int_level &= ~ PL011_INT_RX;
s->int_level &= ~ INT_RX;
trace_pl011_read_fifo(s->read_count);
s->rsr = c >> 8;
pl011_update(s);
@ -191,7 +214,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
break;
}
trace_pl011_read(offset, r);
trace_pl011_read(offset, r, pl011_regname(offset));
return r;
}
@ -202,7 +225,7 @@ static void pl011_set_read_trigger(PL011State *s)
the threshold. However linux only reads the FIFO in response to an
interrupt. Triggering the interrupt when the FIFO is non-empty seems
to make things work. */
if (s->lcr & 0x10)
if (s->lcr & LCR_FEN)
s->read_trigger = (s->ifl >> 1) & 0x1c;
else
#endif
@ -234,7 +257,7 @@ static void pl011_write(void *opaque, hwaddr offset,
PL011State *s = (PL011State *)opaque;
unsigned char ch;
trace_pl011_write(offset, value);
trace_pl011_write(offset, value, pl011_regname(offset));
switch (offset >> 2) {
case 0: /* UARTDR */
@ -243,7 +266,7 @@ static void pl011_write(void *opaque, hwaddr offset,
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->int_level |= PL011_INT_TX;
s->int_level |= INT_TX;
pl011_update(s);
break;
case 1: /* UARTRSR/UARTECR */
@ -252,7 +275,7 @@ static void pl011_write(void *opaque, hwaddr offset,
case 6: /* UARTFR */
/* Writes to Flag register are ignored. */
break;
case 8: /* UARTUARTILPR */
case 8: /* UARTILPR */
s->ilpr = value;
break;
case 9: /* UARTIBRD */
@ -265,11 +288,11 @@ static void pl011_write(void *opaque, hwaddr offset,
break;
case 11: /* UARTLCR_H */
/* Reset the FIFO state on FIFO enable or disable */
if ((s->lcr ^ value) & 0x10) {
if ((s->lcr ^ value) & LCR_FEN) {
pl011_reset_fifo(s);
}
if ((s->lcr ^ value) & 0x1) {
int break_enable = value & 0x1;
if ((s->lcr ^ value) & LCR_BRK) {
int break_enable = value & LCR_BRK;
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enable);
}
@ -331,7 +354,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
s->flags |= PL011_FLAG_RXFF;
}
if (s->read_count == s->read_trigger) {
s->int_level |= PL011_INT_RX;
s->int_level |= INT_RX;
pl011_update(s);
}
}
@ -343,8 +366,9 @@ static void pl011_receive(void *opaque, const uint8_t *buf, int size)
static void pl011_event(void *opaque, QEMUChrEvent event)
{
if (event == CHR_EVENT_BREAK)
pl011_put_fifo(opaque, 0x400);
if (event == CHR_EVENT_BREAK) {
pl011_put_fifo(opaque, DR_BE);
}
}
static void pl011_clock_update(void *opaque, ClockEvent event)
@ -358,6 +382,8 @@ static const MemoryRegionOps pl011_ops = {
.read = pl011_read,
.write = pl011_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
};
static bool pl011_clock_needed(void *opaque)

2
hw/char/serial.c
View File

@ -226,7 +226,7 @@ static gboolean serial_watch_cb(void *do_not_use, GIOCondition cond,
SerialState *s = opaque;
s->watch_tag = 0;
serial_xmit(s);
return FALSE;
return G_SOURCE_REMOVE;
}
static void serial_xmit(SerialState *s)

4
hw/char/trace-events
View File

@ -54,9 +54,9 @@ escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=0x%0
# pl011.c
pl011_irq_state(int level) "irq state %d"
pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s"
pl011_read_fifo(int read_count) "FIFO read, read_count now %d"
pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s"
pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d"
pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d"
pl011_put_fifo_full(void) "FIFO now full, RXFF set"

2
hw/char/virtio-console.c
View File

@ -45,7 +45,7 @@ static gboolean chr_write_unblocked(void *do_not_use, GIOCondition cond,
vcon->watch = 0;
virtio_serial_throttle_port(VIRTIO_SERIAL_PORT(vcon), false);
return FALSE;
return G_SOURCE_REMOVE;
}
/* Callback function that's called when the guest sends us data */

2
hw/display/bochs-display.c
View File

@ -164,7 +164,7 @@ static int bochs_display_get_mode(BochsDisplayState *s,
memset(mode, 0, sizeof(*mode));
switch (vbe[VBE_DISPI_INDEX_BPP]) {
case 16:
/* best effort: support native endianess only */
/* best effort: support native endianness only */
mode->format = PIXMAN_r5g6b5;
mode->bytepp = 2;
break;

2
hw/display/qxl.c
View File

@ -1544,7 +1544,7 @@ static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
}
}
/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
/* return 1 if surface destroy was initiated (in QXL_ASYNC case) or
* done (in QXL_SYNC case), 0 otherwise. */
static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
{

2
hw/display/ssd0303.c
View File

@ -8,7 +8,7 @@
*/
/* The controller can support a variety of different displays, but we only
implement one. Most of the commends relating to brightness and geometry
implement one. Most of the commands relating to brightness and geometry
setup are ignored. */
#include "qemu/osdep.h"

2
hw/display/ssd0323.c
View File

@ -8,7 +8,7 @@
*/
/* The controller can support a variety of different displays, but we only
implement one. Most of the commends relating to brightness and geometry
implement one. Most of the commands relating to brightness and geometry
setup are ignored. */
#include "qemu/osdep.h"

2
hw/display/xlnx_dp.c
View File

@ -380,7 +380,7 @@ static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s)
static void xlnx_dp_audio_callback(void *opaque, int avail)
{
/*
* Get some data from the DPDMA and compute these datas.
* Get some data from the DPDMA and compute these data.
* Then wait for QEMU's audio subsystem to call this callback.
*/
XlnxDPState *s = XLNX_DP(opaque);

1
hw/dma/etraxfs_dma.c
View File

@ -28,6 +28,7 @@
#include "qemu/main-loop.h"
#include "sysemu/runstate.h"
#include "exec/address-spaces.h"
#include "exec/memory.h"
#include "hw/cris/etraxfs_dma.h"

2
hw/i2c/pm_smbus.c
View File

@ -1,6 +1,6 @@
/*
* PC SMBus implementation
* splitted from acpi.c
* split from acpi.c
*
* Copyright (c) 2006 Fabrice Bellard
*

19
hw/i2c/pmbus_device.c
View File

@ -190,15 +190,18 @@ static void pmbus_quick_cmd(SMBusDevice *smd, uint8_t read)
}
}
static uint8_t pmbus_pages_num(PMBusDevice *pmdev)
{
const PMBusDeviceClass *k = PMBUS_DEVICE_GET_CLASS(pmdev);
/* some PMBus devices don't use the PAGE command, so they get 1 page */
return k->device_num_pages ? : 1;
}
static void pmbus_pages_alloc(PMBusDevice *pmdev)
{
/* some PMBus devices don't use the PAGE command, so they get 1 page */
PMBusDeviceClass *k = PMBUS_DEVICE_GET_CLASS(pmdev);
if (k->device_num_pages == 0) {
k->device_num_pages = 1;
}
pmdev->num_pages = k->device_num_pages;
pmdev->pages = g_new0(PMBusPage, k->device_num_pages);
pmdev->num_pages = pmbus_pages_num(pmdev);
pmdev->pages = g_new0(PMBusPage, pmdev->num_pages);
}
void pmbus_check_limits(PMBusDevice *pmdev)
@ -1623,7 +1626,7 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len)
break;
passthrough:
/* Unimplimented registers get passed to the device */
/* Unimplemented registers get passed to the device */
default:
if (pmdc->write_data) {
ret = pmdc->write_data(pmdev, buf, len);

2
hw/i2c/smbus_slave.c
View File

@ -2,7 +2,7 @@
* QEMU SMBus device emulation.
*
* This code is a helper for SMBus device emulation. It implements an
* I2C device inteface and runs the SMBus protocol from the device
* I2C device interface and runs the SMBus protocol from the device
* point of view and maps those to simple calls to emulate.
*
* Copyright (c) 2007 CodeSourcery.

6
hw/i386/kvm/clock.c
View File

@ -22,7 +22,7 @@
#include "kvm/kvm_i386.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/kvm/clock.h"
#include "hw/i386/kvm/clock.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
@ -332,8 +332,10 @@ void kvmclock_create(bool create_always)
{
X86CPU *cpu = X86_CPU(first_cpu);
if (!kvm_enabled() || !kvm_has_adjust_clock())
assert(kvm_enabled());
if (!kvm_has_adjust_clock()) {
return;
}
if (create_always ||
cpu->env.features[FEAT_KVM] & ((1ULL << KVM_FEATURE_CLOCKSOURCE) |

14
include/hw/kvm/clock.h → hw/i386/kvm/clock.h
View File

@ -10,19 +10,9 @@
* See the COPYING file in the top-level directory.
*/
#ifndef HW_KVM_CLOCK_H
#define HW_KVM_CLOCK_H
#ifdef CONFIG_KVM
#ifndef HW_I386_KVM_CLOCK_H
#define HW_I386_KVM_CLOCK_H
void kvmclock_create(bool create_always);
#else /* CONFIG_KVM */
static inline void kvmclock_create(bool create_always)
{
}
#endif /* !CONFIG_KVM */
#endif

6
hw/i386/microvm.c
View File

@ -32,7 +32,7 @@
#include "hw/loader.h"
#include "hw/irq.h"
#include "hw/kvm/clock.h"
#include "hw/i386/kvm/clock.h"
#include "hw/i386/microvm.h"
#include "hw/i386/x86.h"
#include "target/i386/cpu.h"
@ -180,7 +180,9 @@ static void microvm_devices_init(MicrovmMachineState *mms)
x86ms->ioapic2 = ioapic_init_secondary(gsi_state);
}
kvmclock_create(true);
if (kvm_enabled()) {
kvmclock_create(true);
}
mms->virtio_irq_base = 5;
mms->virtio_num_transports = 8;

4
hw/i386/pc_piix.c
View File

@ -46,7 +46,7 @@
#include "hw/ide/piix.h"
#include "hw/irq.h"
#include "sysemu/kvm.h"
#include "hw/kvm/clock.h"
#include "hw/i386/kvm/clock.h"
#include "hw/sysbus.h"
#include "hw/i2c/smbus_eeprom.h"
#include "exec/memory.h"
@ -192,7 +192,7 @@ static void pc_init1(MachineState *machine,
pc_machine_init_sgx_epc(pcms);
x86_cpus_init(x86ms, pcmc->default_cpu_version);
if (pcmc->kvmclock_enabled) {
if (kvm_enabled() && pcmc->kvmclock_enabled) {
kvmclock_create(pcmc->kvmclock_create_always);
}

6
hw/i386/pc_q35.c
View File

@ -35,7 +35,7 @@
#include "hw/i2c/smbus_eeprom.h"
#include "hw/rtc/mc146818rtc.h"
#include "sysemu/kvm.h"
#include "hw/kvm/clock.h"
#include "hw/i386/kvm/clock.h"
#include "hw/pci-host/q35.h"
#include "hw/pci/pcie_port.h"
#include "hw/qdev-properties.h"
@ -183,7 +183,9 @@ static void pc_q35_init(MachineState *machine)
pc_machine_init_sgx_epc(pcms);
x86_cpus_init(x86ms, pcmc->default_cpu_version);
kvmclock_create(pcmc->kvmclock_create_always);
if (kvm_enabled()) {
kvmclock_create(pcmc->kvmclock_create_always);
}
/* pci enabled */
if (pcmc->pci_enabled) {

4
hw/ide/ahci_internal.h
View File

@ -61,13 +61,13 @@ enum AHCIHostReg {
AHCI_HOST_REG_CTL = 1, /* GHC: global host control */
AHCI_HOST_REG_IRQ_STAT = 2, /* IS: interrupt status */
AHCI_HOST_REG_PORTS_IMPL = 3, /* PI: bitmap of implemented ports */
AHCI_HOST_REG_VERSION = 4, /* VS: AHCI spec. version compliancy */
AHCI_HOST_REG_VERSION = 4, /* VS: AHCI spec. version compliance */
AHCI_HOST_REG_CCC_CTL = 5, /* CCC_CTL: CCC Control */
AHCI_HOST_REG_CCC_PORTS = 6, /* CCC_PORTS: CCC Ports */
AHCI_HOST_REG_EM_LOC = 7, /* EM_LOC: Enclosure Mgmt Location */
AHCI_HOST_REG_EM_CTL = 8, /* EM_CTL: Enclosure Mgmt Control */
AHCI_HOST_REG_CAP2 = 9, /* CAP2: host capabilities, extended */
AHCI_HOST_REG_BOHC = 10, /* BOHC: firmare/os handoff ctrl & status */
AHCI_HOST_REG_BOHC = 10, /* BOHC: firmware/os handoff ctrl & status */
AHCI_HOST_REG__COUNT = 11
};

2
hw/ide/cmd646.c
View File

@ -257,7 +257,7 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
if (d->secondary) {
/* XXX: if not enabled, really disable the seconday IDE controller */
/* XXX: if not enabled, really disable the secondary IDE controller */
pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
}

2
hw/ide/core.c
View File

@ -1698,7 +1698,7 @@ static bool cmd_set_features(IDEState *s, uint8_t cmd)
put_le16(identify_data + 63, 0x07);
put_le16(identify_data + 88, 0x3f);
break;
case 0x02: /* sigle word dma mode*/
case 0x02: /* single word dma mode */
put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
put_le16(identify_data + 63, 0x07);
put_le16(identify_data + 88, 0x3f);

3
hw/intc/apic_common.c
View File

@ -28,7 +28,6 @@
#include "hw/intc/kvm_irqcount.h"
#include "trace.h"
#include "hw/boards.h"
#include "sysemu/hax.h"
#include "sysemu/kvm.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
@ -271,7 +270,7 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
/* Note: We need at least 1M to map the VAPIC option ROM */
if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
!hax_enabled() && current_machine->ram_size >= 1024 * 1024) {
current_machine->ram_size >= 1024 * 1024) {
vapic = sysbus_create_simple("kvmvapic", -1, NULL);
}
s->vapic = vapic;

2
hw/mips/malta.c
View File

@ -627,7 +627,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
10, 10, 11, 11 /* PIIX IRQRC[A:D] */
};
/* Bus endianess is always reversed */
/* Bus endianness is always reversed */
#if TARGET_BIG_ENDIAN
#define cpu_to_gt32(x) (x)
#else

1
hw/net/i82596.c
View File

@ -15,6 +15,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "exec/address-spaces.h"
#include "qemu/module.h"
#include "trace.h"
#include "i82596.h"

2
hw/sd/sd.c
View File

@ -1224,7 +1224,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
}
break;
/* Block read commands (Classs 2) */
/* Block read commands (Class 2) */
case 16: /* CMD16: SET_BLOCKLEN */
switch (sd->state) {
case sd_transfer_state:

2
hw/sd/sdhci.c
View File

@ -1811,7 +1811,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
* on i.MX, but since it is not used by QEMU we do not care.
*
* We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
* here becuase it will result in a call to
* here because it will result in a call to
* sdhci_send_command(s) which we don't want.
*
*/

2
hw/sensor/isl_pmbus_vr.c
View File

@ -101,7 +101,7 @@ static void isl_pmbus_vr_exit_reset(Object *obj)
}
}
/* The raa228000 uses different direct mode coefficents from most isl devices */
/* The raa228000 uses different direct mode coefficients from most isl devices */
static void raa228000_exit_reset(Object *obj)
{
PMBusDevice *pmdev = PMBUS_DEVICE(obj);

2
hw/sensor/max34451.c
View File

@ -734,7 +734,7 @@ static void max34451_init(Object *obj)
/*
* get and set the temperature of the internal temperature sensor in
* centidegrees Celcius i.e.: 2500 -> 25.00 C, max is 327.67 C
* centidegrees Celsius i.e.: 2500 -> 25.00 C, max is 327.67 C
*/
for (int i = 0; i < MAX34451_NUM_TEMP_DEVICES; i++) {
object_property_add(obj, "temperature[*]", "uint16",

2
hw/usb/ccid-card-emulated.c
View File

@ -518,7 +518,7 @@ static void emulated_realize(CCIDCardState *base, Error **errp)
goto out2;
}
/* TODO: a passthru backened that works on local machine. third card type?*/
/* TODO: a passthru backend that works on local machine. third card type?*/
if (card->backend == BACKEND_CERTIFICATES) {
if (card->cert1 != NULL && card->cert2 != NULL && card->cert3 != NULL) {
ret = emulated_initialize_vcard_from_certificates(card);

6
hw/usb/hcd-ehci.c
View File

@ -1464,7 +1464,7 @@ static int ehci_process_itd(EHCIState *ehci,
usb_handle_packet(dev, &ehci->ipacket);
usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
} else {
DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
DPRINTF("ISOCH: attempt to address non-iso endpoint\n");
ehci->ipacket.status = USB_RET_NAK;
ehci->ipacket.actual_length = 0;
}
@ -1513,7 +1513,7 @@ static int ehci_process_itd(EHCIState *ehci,
/* This state is the entry point for asynchronous schedule
* processing. Entry here consitutes a EHCI start event state (4.8.5)
* processing. Entry here constitutes a EHCI start event state (4.8.5)
*/
static int ehci_state_waitlisthead(EHCIState *ehci, int async)
{
@ -2458,7 +2458,7 @@ static void usb_ehci_vm_state_change(void *opaque, bool running, RunState state)
/*
* The schedule rebuilt from guest memory could cause the migration dest
* to miss a QH unlink, and fail to cancel packets, since the unlinked QH
* will never have existed on the destination. Therefor we must flush the
* will never have existed on the destination. Therefore we must flush the
* async schedule on savevm to catch any not yet noticed unlinks.
*/
if (state == RUN_STATE_SAVE_VM) {

2
hw/usb/hcd-ohci.c
View File

@ -1355,7 +1355,7 @@ static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) {
return ohci->frt << 31;
}
/* Being in USB operational state guarnatees sof_time was set already. */
/* Being in USB operational state guarantees sof_time was set already. */
tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time;
if (tks < 0) {
tks = 0;

10
hw/usb/hcd-xhci.c
View File

@ -2434,7 +2434,6 @@ static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
{
dma_addr_t ctx;
uint8_t bw_ctx[xhci->numports+1];
DPRINTF("xhci_get_port_bandwidth()\n");
@ -2442,11 +2441,10 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
/* TODO: actually implement real values here */
bw_ctx[0] = 0;
memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
if (dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx),
MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
/* TODO: actually implement real values here. This is 80% for all ports. */
if (stb_dma(xhci->as, ctx, 0, MEMTXATTRS_UNSPECIFIED) != MEMTX_OK ||
dma_memory_set(xhci->as, ctx + 1, 80, xhci->numports,
MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory write failed!\n",
__func__);
return CC_TRB_ERROR;

2
hw/usb/quirks.h
View File

@ -67,7 +67,7 @@ static const struct usb_device_id usbredir_raw_serial_ids[] = {
{ USB_DEVICE(0x10C4, 0x800A) }, /* SPORTident BSM7-D-USB main station */
{ USB_DEVICE(0x10C4, 0x803B) }, /* Pololu USB-serial converter */
{ USB_DEVICE(0x10C4, 0x8044) }, /* Cygnal Debug Adapter */
{ USB_DEVICE(0x10C4, 0x804E) }, /* Software Bisque Paramount ME build-in converter */
{ USB_DEVICE(0x10C4, 0x804E) }, /* Software Bisque Paramount ME built-in converter */
{ USB_DEVICE(0x10C4, 0x8053) }, /* Enfora EDG1228 */
{ USB_DEVICE(0x10C4, 0x8054) }, /* Enfora GSM2228 */
{ USB_DEVICE(0x10C4, 0x8066) }, /* Argussoft In-System Programmer */

4
hw/usb/redirect.c
View File

@ -278,7 +278,7 @@ static gboolean usbredir_write_unblocked(void *do_not_use, GIOCondition cond,
dev->watch = 0;
usbredirparser_do_write(dev->parser);
return FALSE;
return G_SOURCE_REMOVE;
}
static int usbredir_write(void *priv, uint8_t *data, int count)
@ -471,7 +471,7 @@ static int bufp_alloc(USBRedirDevice *dev, uint8_t *data, uint16_t len,
DPRINTF("bufpq overflow, dropping packets ep %02X\n", ep);
dev->endpoint[EP2I(ep)].bufpq_dropping_packets = 1;
}
/* Since we're interupting the stream anyways, drop enough packets to get
/* Since we're interrupting the stream anyways, drop enough packets to get
back to our target buffer size */
if (dev->endpoint[EP2I(ep)].bufpq_dropping_packets) {
if (dev->endpoint[EP2I(ep)].bufpq_size >

2
hw/usb/trace-events
View File

@ -248,7 +248,7 @@ usb_set_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret
# dev-hub.c
usb_hub_reset(int addr) "dev %d"
usb_hub_control(int addr, int request, int value, int index, int length) "dev %d, req 0x%x, value %d, index %d, langth %d"
usb_hub_control(int addr, int request, int value, int index, int length) "dev %d, req 0x%x, value %d, index %d, length %d"
usb_hub_get_port_status(int addr, int nr, int status, int changed) "dev %d, port %d, status 0x%x, changed 0x%x"
usb_hub_set_port_feature(int addr, int nr, const char *f) "dev %d, port %d, feature %s"
usb_hub_clear_port_feature(int addr, int nr, const char *f) "dev %d, port %d, feature %s"

2
hw/usb/xen-usb.c
View File

@ -451,7 +451,7 @@ static int usbback_check_and_submit(struct usbback_req *usbback_req)
wValue = le16_to_cpu(ctrl->wValue);
/*
* When the device is first connected or resetted, USB device has no
* When the device is first connected or reset, USB device has no
* address. In this initial state, following requests are sent to device
* address (#0),
*

8
hw/xen/xen_pt.h
View File

@ -340,11 +340,9 @@ static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
return s->msix && s->msix->bar_index == bar;
}
extern void *pci_assign_dev_load_option_rom(PCIDevice *dev,
int *size,
unsigned int domain,
unsigned int bus, unsigned int slot,
unsigned int function);
void *pci_assign_dev_load_option_rom(PCIDevice *dev, int *size,
unsigned int domain, unsigned int bus,
unsigned int slot, unsigned int function);
static inline bool is_igd_vga_passthrough(XenHostPCIDevice *dev)
{
return (xen_igd_gfx_pt_enabled()

1
hw/xtensa/pic_cpu.c
View File

@ -30,6 +30,7 @@
#include "hw/irq.h"
#include "qemu/log.h"
#include "qemu/timer.h"
#include "qemu/atomic.h"
void check_interrupts(CPUXtensaState *env)
{

14
include/chardev/char-fe.h
View File

@ -175,6 +175,20 @@ void qemu_chr_fe_printf(CharBackend *be, const char *fmt, ...)
G_GNUC_PRINTF(2, 3);
/**
* FEWatchFunc: a #GSourceFunc called when any conditions requested by
* qemu_chr_fe_add_watch() is satisfied.
* @do_not_use: depending on the underlying chardev, a GIOChannel or a
* QIOChannel. DO NOT USE!
* @cond: bitwise combination of conditions watched and satisfied
* before calling this callback.
* @data: user data passed at creation to qemu_chr_fe_add_watch(). Can
* be NULL.
*
* Returns: G_SOURCE_REMOVE if the GSource should be removed from the
* main loop, or G_SOURCE_CONTINUE to leave the GSource in
* the main loop.
*/
typedef gboolean (*FEWatchFunc)(void *do_not_use, GIOCondition condition, void *data);
/**

14
include/crypto/secret_common.h
View File

@ -48,13 +48,11 @@ struct QCryptoSecretCommonClass {
};
extern int qcrypto_secret_lookup(const char *secretid,
uint8_t **data,
size_t *datalen,
Error **errp);
extern char *qcrypto_secret_lookup_as_utf8(const char *secretid,
Error **errp);
extern char *qcrypto_secret_lookup_as_base64(const char *secretid,
Error **errp);
int qcrypto_secret_lookup(const char *secretid,
uint8_t **data,
size_t *datalen,
Error **errp);
char *qcrypto_secret_lookup_as_utf8(const char *secretid, Error **errp);
char *qcrypto_secret_lookup_as_base64(const char *secretid, Error **errp);
#endif /* QCRYPTO_SECRET_COMMON_H */

4
include/elf.h
View File

@ -1125,9 +1125,9 @@ typedef struct {
#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */
#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */
/* Additional section indeces. */
/* Additional section indices. */
#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared
#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tentatively declared
symbols in ANSI C. */
#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */

2
include/exec/address-spaces.h
View File

@ -19,8 +19,6 @@
* you're one of them.
*/
#include "exec/memory.h"
#ifndef CONFIG_USER_ONLY
/* Get the root memory region. This interface should only be used temporarily

2
include/exec/exec-all.h
View File

@ -21,7 +21,7 @@
#define EXEC_ALL_H
#include "cpu.h"
#ifdef CONFIG_TCG
#if defined(CONFIG_USER_ONLY)
#include "exec/cpu_ldst.h"
#endif
#include "exec/translation-block.h"

42
include/exec/memory_ldst.h.inc
View File

@ -20,48 +20,48 @@
*/
#ifdef TARGET_ENDIANNESS
extern uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw, SUFFIX)(ARG1_DECL,
void glue(address_space_stw, SUFFIX)(ARG1_DECL,
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl, SUFFIX)(ARG1_DECL,
void glue(address_space_stl, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stq, SUFFIX)(ARG1_DECL,
void glue(address_space_stq, SUFFIX)(ARG1_DECL,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result);
#else
extern uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL,
uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stb, SUFFIX)(ARG1_DECL,
void glue(address_space_stb, SUFFIX)(ARG1_DECL,
hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stq_le, SUFFIX)(ARG1_DECL,
void glue(address_space_stq_le, SUFFIX)(ARG1_DECL,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stq_be, SUFFIX)(ARG1_DECL,
void glue(address_space_stq_be, SUFFIX)(ARG1_DECL,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result);
#endif

4
include/exec/page-vary.h
View File

@ -27,8 +27,8 @@ typedef struct {
} TargetPageBits;
#ifdef IN_PAGE_VARY
extern bool set_preferred_target_page_bits_common(int bits);
extern void finalize_target_page_bits_common(int min);
bool set_preferred_target_page_bits_common(int bits);
void finalize_target_page_bits_common(int min);
#endif
/**

1
include/exec/poison.h
View File

@ -81,7 +81,6 @@
#pragma GCC poison CONFIG_SPARC_DIS
#pragma GCC poison CONFIG_XTENSA_DIS
#pragma GCC poison CONFIG_HAX
#pragma GCC poison CONFIG_HVF
#pragma GCC poison CONFIG_LINUX_USER
#pragma GCC poison CONFIG_KVM

6
include/exec/translation-block.h
View File

@ -7,11 +7,11 @@
#ifndef EXEC_TRANSLATION_BLOCK_H
#define EXEC_TRANSLATION_BLOCK_H
#include "qemu/atomic.h"
#include "qemu/thread.h"
#include "qemu/interval-tree.h"
#include "exec/cpu-common.h"
#include "exec/target_page.h"
#ifdef CONFIG_USER_ONLY
#include "qemu/interval-tree.h"
#endif
/*
* Page tracking code uses ram addresses in system mode, and virtual

2
include/hw/core/cpu.h
View File

@ -422,7 +422,7 @@ struct CPUState {
int32_t exception_index;
AccelCPUState *accel;
/* shared by kvm, hax and hvf */
/* shared by kvm and hvf */
bool vcpu_dirty;
/* Used to keep track of an outstanding cpu throttle thread for migration

2
include/hw/core/tcg-cpu-ops.h
View File

@ -14,7 +14,7 @@
struct TCGCPUOps {
/**
* @initialize: Initalize TCG state
* @initialize: Initialize TCG state
*
* Called when the first CPU is realized.
*/

2
include/hw/i2c/npcm7xx_smbus.h
View File

@ -58,7 +58,7 @@ typedef enum NPCM7xxSMBusStatus {
* @sclht: The SCL high time register.
* @fif_ctl: The FIFO control register.
* @fif_cts: The FIFO control status register.
* @fair_per: The fair preriod register.
* @fair_per: The fair period register.
* @txf_ctl: The transmit FIFO control register.
* @t_out: The SMBus timeout register.
* @txf_sts: The transmit FIFO status register.

2
include/hw/misc/aspeed_scu.h
View File

@ -51,7 +51,7 @@ struct AspeedSCUState {
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
bool is_supported_silicon_rev(uint32_t silicon_rev);
struct AspeedSCUClass {

2
include/hw/misc/auxbus.h
View File

@ -106,7 +106,7 @@ void aux_bus_realize(AUXBus *bus);
*
* Returns the reply of the request.
*
* @bus Ths bus where the request happen.
* @bus The bus where the request happen.
* @cmd The command requested.
* @address The 20bits address of the slave.
* @len The length of the read or write.

4
include/hw/nvram/npcm7xx_otp.h
View File

@ -73,7 +73,7 @@ typedef struct NPCM7xxOTPClass NPCM7xxOTPClass;
* Each nibble of data is encoded into a byte, so the number of bytes written
* to the array will be @len * 2.
*/
extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
unsigned int offset, unsigned int len);
void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
unsigned int offset, unsigned int len);
#endif /* NPCM7XX_OTP_H */

4
include/hw/qdev-core.h
View File

@ -1086,7 +1086,7 @@ typedef enum MachineInitPhase {
PHASE_MACHINE_READY,
} MachineInitPhase;
extern bool phase_check(MachineInitPhase phase);
extern void phase_advance(MachineInitPhase phase);
bool phase_check(MachineInitPhase phase);
void phase_advance(MachineInitPhase phase);
#endif

4
include/io/channel-socket.h
View File

@ -124,7 +124,7 @@ void qio_channel_socket_connect_async(QIOChannelSocket *ioc,
* qio_channel_socket_listen_sync:
* @ioc: the socket channel object
* @addr: the address to listen to
* @num: the expected ammount of connections
* @num: the expected amount of connections
* @errp: pointer to a NULL-initialized error object
*
* Attempt to listen to the address @addr. This method
@ -141,7 +141,7 @@ int qio_channel_socket_listen_sync(QIOChannelSocket *ioc,
* qio_channel_socket_listen_async:
* @ioc: the socket channel object
* @addr: the address to listen to
* @num: the expected ammount of connections
* @num: the expected amount of connections
* @callback: the function to invoke on completion
* @opaque: user data to pass to @callback
* @destroy: the function to free @opaque

2
include/io/task.h
View File

@ -145,7 +145,7 @@ typedef void (*QIOTaskWorker)(QIOTask *task,
* The QIOTask module can also be used to perform operations
* in a background thread context, while still reporting the
* results in the main event thread. This allows code which
* cannot easily be rewritten to be asychronous (such as DNS
* cannot easily be rewritten to be asynchronous (such as DNS
* lookups) to be easily run non-blocking. Reporting the
* results in the main thread context means that the caller
* typically does not need to be concerned about thread

4
include/qemu/crc-ccitt.h
View File

@ -17,8 +17,8 @@
extern uint16_t const crc_ccitt_table[256];
extern uint16_t const crc_ccitt_false_table[256];
extern uint16_t crc_ccitt(uint16_t crc, const uint8_t *buffer, size_t len);
extern uint16_t crc_ccitt_false(uint16_t crc, const uint8_t *buffer, size_t len);
uint16_t crc_ccitt(uint16_t crc, const uint8_t *buffer, size_t len);
uint16_t crc_ccitt_false(uint16_t crc, const uint8_t *buffer, size_t len);
static inline uint16_t crc_ccitt_byte(uint16_t crc, const uint8_t c)
{

2
include/qemu/fifo8.h
View File

@ -46,7 +46,7 @@ void fifo8_push(Fifo8 *fifo, uint8_t data);
* fifo8_push_all:
* @fifo: FIFO to push to
* @data: data to push
* @size: number of bytes to push
* @num: number of bytes to push
*
* Push a byte array to the FIFO. Behaviour is undefined if the FIFO is full.
* Clients are responsible for checking the space left in the FIFO using

4
include/qemu/iova-tree.h
View File

@ -15,7 +15,7 @@
* Currently the iova tree will only allow to keep ranges
* information, and no extra user data is allowed for each element. A
* benefit is that we can merge adjacent ranges internally within the
* tree. It can save a lot of memory when the ranges are splitted but
* tree. It can save a lot of memory when the ranges are split but
* mostly continuous.
*
* Note that current implementation does not provide any thread
@ -128,7 +128,7 @@ const DMAMap *iova_tree_find_address(const IOVATree *tree, hwaddr iova);
* iova_tree_foreach:
*
* @tree: the iova tree to iterate on
* @iterator: the interator for the mappings, return true to stop
* @iterator: the iterator for the mappings, return true to stop
*
* Iterate over the iova tree.
*

4
include/qemu/osdep.h
View File

@ -250,7 +250,7 @@ extern "C" {
* supports QEMU_ERROR, this will be reported at compile time; otherwise
* this will be reported at link time due to the missing symbol.
*/
G_NORETURN extern
G_NORETURN
void QEMU_ERROR("code path is reachable")
qemu_build_not_reached_always(void);
#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__)
@ -506,7 +506,7 @@ void qemu_anon_ram_free(void *ptr, size_t size);
* See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for discussion
* about Solaris missing the madvise() prototype.
*/
extern int madvise(char *, size_t, int);
int madvise(char *, size_t, int);
#endif
#if defined(CONFIG_LINUX)

2
include/qemu/processor.h
View File

@ -7,8 +7,6 @@
#ifndef QEMU_PROCESSOR_H
#define QEMU_PROCESSOR_H
#include "qemu/atomic.h"
#if defined(__i386__) || defined(__x86_64__)
# define cpu_relax() asm volatile("rep; nop" ::: "memory")

14
include/qemu/rcu.h
View File

@ -118,19 +118,19 @@ static inline void rcu_read_unlock(void)
}
}
extern void synchronize_rcu(void);
void synchronize_rcu(void);
/*
* Reader thread registration.
*/
extern void rcu_register_thread(void);
extern void rcu_unregister_thread(void);
void rcu_register_thread(void);
void rcu_unregister_thread(void);
/*
* Support for fork(). fork() support is enabled at startup.
*/
extern void rcu_enable_atfork(void);
extern void rcu_disable_atfork(void);
void rcu_enable_atfork(void);
void rcu_disable_atfork(void);
struct rcu_head;
typedef void RCUCBFunc(struct rcu_head *head);
@ -140,8 +140,8 @@ struct rcu_head {
RCUCBFunc *func;
};
extern void call_rcu1(struct rcu_head *head, RCUCBFunc *func);
extern void drain_call_rcu(void);
void call_rcu1(struct rcu_head *head, RCUCBFunc *func);
void drain_call_rcu(void);
/* The operands of the minus operator must have the same type,
* which must be the one that we specify in the cast.

4
include/qemu/sys_membarrier.h
View File

@ -14,8 +14,8 @@
* side. The slow side forces processor-level ordering on all other cores
* through a system call.
*/
extern void smp_mb_global_init(void);
extern void smp_mb_global(void);
void smp_mb_global_init(void);
void smp_mb_global(void);
#define smp_mb_placeholder() barrier()
#else
/* Keep it simple, execute a real memory barrier on both sides. */

6
include/qemu/uri.h
View File

@ -96,8 +96,8 @@ typedef struct QueryParams {
QueryParam *p; /* array of parameters */
} QueryParams;
struct QueryParams *query_params_new (int init_alloc);
extern QueryParams *query_params_parse (const char *query);
extern void query_params_free (QueryParams *ps);
QueryParams *query_params_new(int init_alloc);
QueryParams *query_params_parse(const char *query);
void query_params_free(QueryParams *ps);
#endif /* QEMU_URI_H */

2
include/qemu/yank.h
View File

@ -25,7 +25,7 @@ typedef void (YankFn)(void *opaque);
* @instance: The instance.
* @errp: Error object.
*
* Returns true on success or false if an error occured.
* Returns true on success or false if an error occurred.
*/
bool yank_register_instance(const YankInstance *instance, Error **errp);

14
include/sysemu/accel-blocker.h
View File

@ -16,7 +16,7 @@
#include "sysemu/cpus.h"
extern void accel_blocker_init(void);
void accel_blocker_init(void);
/*
* accel_{cpu_}ioctl_begin/end:
@ -26,10 +26,10 @@ extern void accel_blocker_init(void);
* called, preventing new ioctls to run. They will continue only after
* accel_ioctl_inibith_end().
*/
extern void accel_ioctl_begin(void);
extern void accel_ioctl_end(void);
extern void accel_cpu_ioctl_begin(CPUState *cpu);
extern void accel_cpu_ioctl_end(CPUState *cpu);
void accel_ioctl_begin(void);
void accel_ioctl_end(void);
void accel_cpu_ioctl_begin(CPUState *cpu);
void accel_cpu_ioctl_end(CPUState *cpu);
/*
* accel_ioctl_inhibit_begin: start critical section
@ -42,7 +42,7 @@ extern void accel_cpu_ioctl_end(CPUState *cpu);
* This allows the caller to access shared data or perform operations without
* worrying of concurrent vcpus accesses.
*/
extern void accel_ioctl_inhibit_begin(void);
void accel_ioctl_inhibit_begin(void);
/*
* accel_ioctl_inhibit_end: end critical section started by
@ -50,6 +50,6 @@ extern void accel_ioctl_inhibit_begin(void);
*
* This function allows blocked accel_{cpu_}ioctl_begin() to continue.
*/
extern void accel_ioctl_inhibit_end(void);
void accel_ioctl_inhibit_end(void);
#endif /* ACCEL_BLOCKER_H */

49
include/sysemu/hax.h
View File

@ -1,49 +0,0 @@
/*
* QEMU HAXM support
*
* Copyright IBM, Corp. 2008
*
* Authors:
* Anthony Liguori <aliguori@us.ibm.com>
*
* Copyright (c) 2011 Intel Corporation
* Written by:
* Jiang Yunhong<yunhong.jiang@intel.com>
* Xin Xiaohui<xiaohui.xin@intel.com>
* Zhang Xiantao<xiantao.zhang@intel.com>
*
* Copyright 2016 Google, Inc.
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
*/
/* header to be included in non-HAX-specific code */
#ifndef QEMU_HAX_H
#define QEMU_HAX_H
int hax_sync_vcpus(void);
#ifdef NEED_CPU_H
# ifdef CONFIG_HAX
# define CONFIG_HAX_IS_POSSIBLE
# endif
#else /* !NEED_CPU_H */
# define CONFIG_HAX_IS_POSSIBLE
#endif
#ifdef CONFIG_HAX_IS_POSSIBLE
extern bool hax_allowed;
#define hax_enabled() (hax_allowed)
#else /* !CONFIG_HAX_IS_POSSIBLE */
#define hax_enabled() (0)
#endif /* CONFIG_HAX_IS_POSSIBLE */
#endif /* QEMU_HAX_H */

1
include/sysemu/hw_accel.h
View File

@ -12,7 +12,6 @@
#define QEMU_HW_ACCEL_H
#include "hw/core/cpu.h"
#include "sysemu/hax.h"
#include "sysemu/kvm.h"
#include "sysemu/hvf.h"
#include "sysemu/whpx.h"

4
include/sysemu/os-win32.h
View File

@ -66,8 +66,8 @@ extern "C" {
* setjmp to _setjmpex instead. However, they are still defined in libmingwex.a,
* which gets linked automatically.
*/
extern int __mingw_setjmp(jmp_buf);
extern void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int);
int __mingw_setjmp(jmp_buf);
void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int);
#define setjmp(env) __mingw_setjmp(env)
#define longjmp(env, val) __mingw_longjmp(env, val)
#elif defined(_WIN64)

2
include/tcg/helper-info.h
View File

@ -1,5 +1,5 @@
/*
* TCG Helper Infomation Structure
* TCG Helper Information Structure
*
* Copyright (c) 2023 Linaro Ltd
*

4
include/tcg/tcg.h
View File

@ -879,7 +879,7 @@ enum {
/* Instruction operands are 64-bits (otherwise 32-bits). */
TCG_OPF_64BIT = 0x10,
/* Instruction is optional and not implemented by the host, or insn
is generic and should not be implemened by the host. */
is generic and should not be implemented by the host. */
TCG_OPF_NOT_PRESENT = 0x20,
/* Instruction operands are vectors. */
TCG_OPF_VECTOR = 0x40,
@ -1123,7 +1123,7 @@ static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
/* Expand the tuple (opc, type, vece) on the given arguments. */
void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
/* Replicate a constant C accoring to the log2 of the element size. */
/* Replicate a constant C according to the log2 of the element size. */
uint64_t dup_const(unsigned vece, uint64_t c);
#define dup_const(VECE, C) \

2
include/ui/kbd-state.h
View File

@ -65,7 +65,7 @@ void qkbd_state_key_event(QKbdState *kbd, QKeyCode qcode, bool down);
* using qemu_input_event_send_key_delay().
*
* @kbd: state tracker state.
* @delay_ms: the delay in miliseconds.
* @delay_ms: the delay in milliseconds.
*/
void qkbd_state_set_delay(QKbdState *kbd, int delay_ms);

2
include/ui/spice-display.h
View File

@ -42,7 +42,7 @@
#define NUM_MEMSLOTS_GROUPS 2
/*
* Internal enum to differenciate between options for
* Internal enum to differentiate between options for
* io calls that have a sync (old) version and an _async (new)
* version:
* QXL_SYNC: use the old version

6
include/user/safe-syscall.h
View File

@ -91,7 +91,7 @@
*
* The basic setup is that we make the host syscall via a known
* section of host native assembly. If a signal occurs, our signal
* handler checks the interrupted host PC against the addresse of that
* handler checks the interrupted host PC against the address of that
* known section. If the PC is before or at the address of the syscall
* instruction then we change the PC to point at a "return
* -QEMU_ERESTARTSYS" code path instead, and then exit the signal handler
@ -126,8 +126,8 @@
*/
/* The core part of this function is implemented in assembly */
extern long safe_syscall_base(int *pending, long number, ...);
extern long safe_syscall_set_errno_tail(int value);
long safe_syscall_base(int *pending, long number, ...);
long safe_syscall_set_errno_tail(int value);
/* These are defined by the safe-syscall.inc.S file */
extern char safe_syscall_start[];

2
linux-user/flatload.c
View File

@ -780,7 +780,7 @@ int load_flt_binary(struct linux_binprm *bprm, struct image_info *info)
/* Enforce final stack alignment of 16 bytes. This is sufficient
for all current targets, and excess alignment is harmless. */
stack_len = bprm->envc + bprm->argc + 2;
stack_len += flat_argvp_envp_on_stack() ? 2 : 0; /* arvg, argp */
stack_len += flat_argvp_envp_on_stack() ? 2 : 0; /* argv, argp */
stack_len += 1; /* argc */
stack_len *= sizeof(abi_ulong);
sp -= (sp - stack_len) & 15;

4
linux-user/syscall.c
View File

@ -1809,7 +1809,7 @@ static inline abi_long target_to_host_cmsg(struct msghdr *msgh,
uint32_t *dst = (uint32_t *)data;
memcpy(dst, target_data, len);
/* fix endianess of first 32-bit word */
/* fix endianness of first 32-bit word */
if (len >= sizeof(uint32_t)) {
*dst = tswap32(*dst);
}
@ -2920,7 +2920,7 @@ get_timeout:
unlock_user(results, optval_addr, 0);
return ret;
}
/* swap host endianess to target endianess. */
/* swap host endianness to target endianness. */
for (i = 0; i < (len / sizeof(uint32_t)); i++) {
results[i] = tswap32(results[i]);
}

11
meson.build
View File

@ -140,7 +140,6 @@ if cpu in ['x86', 'x86_64', 'arm', 'aarch64']
endif
if cpu in ['x86', 'x86_64']
accelerator_targets += {
'CONFIG_HAX': ['i386-softmmu', 'x86_64-softmmu'],
'CONFIG_HVF': ['x86_64-softmmu'],
'CONFIG_NVMM': ['i386-softmmu', 'x86_64-softmmu'],
'CONFIG_WHPX': ['i386-softmmu', 'x86_64-softmmu'],
@ -224,7 +223,9 @@ qemu_ldflags = []
if targetos == 'darwin'
# Disable attempts to use ObjectiveC features in os/object.h since they
# won't work when we're compiling with gcc as a C compiler.
qemu_common_flags += '-DOS_OBJECT_USE_OBJC=0'
if compiler.get_id() == 'gcc'
qemu_common_flags += '-DOS_OBJECT_USE_OBJC=0'
endif
elif targetos == 'solaris'
# needed for CMSG_ macros in sys/socket.h
qemu_common_flags += '-D_XOPEN_SOURCE=600'
@ -663,11 +664,6 @@ if get_option('hvf').allowed()
accelerators += 'CONFIG_HVF'
endif
endif
if get_option('hax').allowed()
if get_option('hax').enabled() or targetos in ['windows', 'darwin', 'netbsd']
accelerators += 'CONFIG_HAX'
endif
endif
if targetos == 'netbsd'
nvmm = cc.find_library('nvmm', required: get_option('nvmm'))
if nvmm.found()
@ -4140,7 +4136,6 @@ endif
summary_info = {}
if have_system
summary_info += {'KVM support': config_all.has_key('CONFIG_KVM')}
summary_info += {'HAX support': config_all.has_key('CONFIG_HAX')}
summary_info += {'HVF support': config_all.has_key('CONFIG_HVF')}
summary_info += {'WHPX support': config_all.has_key('CONFIG_WHPX')}
summary_info += {'NVMM support': config_all.has_key('CONFIG_NVMM')}

2
meson_options.txt
View File

@ -69,8 +69,6 @@ option('malloc', type : 'combo', choices : ['system', 'tcmalloc', 'jemalloc'],
option('kvm', type: 'feature', value: 'auto',
description: 'KVM acceleration support')
option('hax', type: 'feature', value: 'auto',
description: 'HAX acceleration support')
option('whpx', type: 'feature', value: 'auto',
description: 'WHPX acceleration support')
option('hvf', type: 'feature', value: 'auto',

2
monitor/monitor.c
View File

@ -144,7 +144,7 @@ static gboolean monitor_unblocked(void *do_not_use, GIOCondition cond,
QEMU_LOCK_GUARD(&mon->mon_lock);
mon->out_watch = 0;
monitor_flush_locked(mon);
return FALSE;
return G_SOURCE_REMOVE;
}
/* Caller must hold mon->mon_lock */

2
net/vhost-user.c
View File

@ -239,7 +239,7 @@ static gboolean net_vhost_user_watch(void *do_not_use, GIOCondition cond,
qemu_chr_fe_disconnect(&s->chr);
return TRUE;
return G_SOURCE_CONTINUE;
}
static void net_vhost_user_event(void *opaque, QEMUChrEvent event);

8
qemu-options.hx
View File

@ -26,7 +26,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \
"-machine [type=]name[,prop[=value][,...]]\n"
" selects emulated machine ('-machine help' for list)\n"
" property accel=accel1[:accel2[:...]] selects accelerator\n"
" supported accelerators are kvm, xen, hax, hvf, nvmm, whpx or tcg (default: tcg)\n"
" supported accelerators are kvm, xen, hvf, nvmm, whpx or tcg (default: tcg)\n"
" vmport=on|off|auto controls emulation of vmport (default: auto)\n"
" dump-guest-core=on|off include guest memory in a core dump (default=on)\n"
" mem-merge=on|off controls memory merge support (default: on)\n"
@ -59,7 +59,7 @@ SRST
``accel=accels1[:accels2[:...]]``
This is used to enable an accelerator. Depending on the target
architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be available.
architecture, kvm, xen, hvf, nvmm, whpx or tcg can be available.
By default, tcg is used. If there is more than one accelerator
specified, the next one is used if the previous one fails to
initialize.
@ -178,7 +178,7 @@ ERST
DEF("accel", HAS_ARG, QEMU_OPTION_accel,
"-accel [accel=]accelerator[,prop[=value][,...]]\n"
" select accelerator (kvm, xen, hax, hvf, nvmm, whpx or tcg; use 'help' for a list)\n"
" select accelerator (kvm, xen, hvf, nvmm, whpx or tcg; use 'help' for a list)\n"
" igd-passthru=on|off (enable Xen integrated Intel graphics passthrough, default=off)\n"
" kernel-irqchip=on|off|split controls accelerated irqchip support (default=on)\n"
" kvm-shadow-mem=size of KVM shadow MMU in bytes\n"
@ -191,7 +191,7 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel,
SRST
``-accel name[,prop=value[,...]]``
This is used to enable an accelerator. Depending on the target
architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be available. By
architecture, kvm, xen, hvf, nvmm, whpx or tcg can be available. By
default, tcg is used. If there is more than one accelerator
specified, the next one is used if the previous one fails to
initialize.

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