From a9c37abdff65a07d0191123a21d318c4d8cc7f33 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 21 Jun 2023 16:23:02 +0200 Subject: [PATCH] target/tricore: Fix ICR.IE offset in RESTORE insn from ISA v1.6.1 onwards the bit position of ICR.IE changed. ctx->icr_ie_offset contains the correct value for the ISA version used by the vCPU. We also need to exit this tb here, as we might have enabled interrupts. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Message-Id: <20230621142302.1648383-9-kbastian@mail.uni-paderborn.de> --- target/tricore/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 9e408f44ec..2f32463d4d 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -7964,7 +7964,9 @@ static void decode_sys_interrupts(DisasContext *ctx) case OPC2_32_SYS_RESTORE: if (has_feature(ctx, TRICORE_FEATURE_16)) { if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { - tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); + tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], + ctx->icr_ie_offset, 1); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } else { generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); }