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hw/mips/gt64xxx: Remove dynamic field width from trace events

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Since not all trace backends support dynamic field width in
format (dtrace via stap does not), replace by a static field
width instead.

We previously passed to the trace API 'width << 1' as the number
of hex characters to display (the dynamic field width). We don't
need this anymore. Instead, display the size of bytes accessed.

Fixes: ab6bff424f ("gt64xxx_pci: Convert debug printf to trace events")
Reported-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Buglink: https://bugs.launchpad.net/qemu/+bug/1844817
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2019-11-08 15:13:59 +01:00
parent 10f9f1fbed
commit abc7cf3655
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
hw/mips/gt64xxx_pci.c
View File

@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* not really implemented */
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
trace_gt64120_write("INTRCAUSE", size << 1, val);
trace_gt64120_write("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
s->regs[saddr] = val & 0x3c3ffffe;
trace_gt64120_write("INTRMASK", size << 1, val);
trace_gt64120_write("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
s->regs[saddr] = val & 0x03fffffe;
trace_gt64120_write("ICMASK", size << 1, val);
trace_gt64120_write("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
s->regs[saddr] = val & 0x0000003f;
trace_gt64120_write("SERR0MASK", size << 1, val);
trace_gt64120_write("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */
@ -930,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque,
/* Interrupts */
case GT_INTRCAUSE:
val = s->regs[saddr];
trace_gt64120_read("INTRCAUSE", size << 1, val);
trace_gt64120_read("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
val = s->regs[saddr];
trace_gt64120_read("INTRMASK", size << 1, val);
trace_gt64120_read("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
val = s->regs[saddr];
trace_gt64120_read("ICMASK", size << 1, val);
trace_gt64120_read("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
val = s->regs[saddr];
trace_gt64120_read("SERR0MASK", size << 1, val);
trace_gt64120_read("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */

4
hw/mips/trace-events
View File

@ -1,4 +1,4 @@
# gt64xxx.c
gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64
gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64
gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64