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target-alpha: Implement rs/rc properly.

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This is a per-cpu flag; there's no need for a spinlock of any kind.

We were also failing to manipulate the flag with $31 as a target reg
and failing to clear the flag on execution of a return-from-interrupt
instruction.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Richard Henderson 2010-04-12 16:14:54 -07:00 committed by Aurelien Jarno
parent dc96be4b97
commit ac316ca4b7
4 changed files with 23 additions and 33 deletions
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7
linux-user/main.c
View File

@ -2358,6 +2358,11 @@ void cpu_loop (CPUState *env)
while (1) {
trapnr = cpu_alpha_exec (env);
/* All of the traps imply a transition through PALcode, which
implies an REI instruction has been executed. Which means
that the intr_flag should be cleared. */
env->intr_flag = 0;
switch (trapnr) {
case EXCP_RESET:
fprintf(stderr, "Reset requested. Exit\n");
@ -2444,7 +2449,7 @@ void cpu_loop (CPUState *env)
env->ir[IR_A0], env->ir[IR_A1],
env->ir[IR_A2], env->ir[IR_A3],
env->ir[IR_A4], env->ir[IR_A5]);
if (trapnr != TARGET_NR_sigreturn
if (trapnr != TARGET_NR_sigreturn
&& trapnr != TARGET_NR_rt_sigreturn) {
env->ir[IR_V0] = (sysret < 0 ? -sysret : sysret);
env->ir[IR_A3] = (sysret < 0);

2
target-alpha/helper.h
View File

@ -2,8 +2,6 @@
DEF_HELPER_2(excp, void, int, int)
DEF_HELPER_FLAGS_0(load_pcc, TCG_CALL_CONST | TCG_CALL_PURE, i64)
DEF_HELPER_FLAGS_0(rc, TCG_CALL_CONST, i64)
DEF_HELPER_FLAGS_0(rs, TCG_CALL_CONST, i64)
DEF_HELPER_2(addqv, i64, i64, i64)
DEF_HELPER_2(addlv, i64, i64, i64)

28
target-alpha/op_helper.c
View File

@ -47,32 +47,6 @@ void helper_store_fpcr (uint64_t val)
cpu_alpha_store_fpcr (env, val);
}
static spinlock_t intr_cpu_lock = SPIN_LOCK_UNLOCKED;
uint64_t helper_rs(void)
{
uint64_t tmp;
spin_lock(&intr_cpu_lock);
tmp = env->intr_flag;
env->intr_flag = 1;
spin_unlock(&intr_cpu_lock);
return tmp;
}
uint64_t helper_rc(void)
{
uint64_t tmp;
spin_lock(&intr_cpu_lock);
tmp = env->intr_flag;
env->intr_flag = 0;
spin_unlock(&intr_cpu_lock);
return tmp;
}
uint64_t helper_addqv (uint64_t op1, uint64_t op2)
{
uint64_t tmp = op1;
@ -1191,6 +1165,7 @@ void helper_hw_rei (void)
{
env->pc = env->ipr[IPR_EXC_ADDR] & ~3;
env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
env->intr_flag = 0;
/* XXX: re-enable interrupts and memory mapping */
}
@ -1198,6 +1173,7 @@ void helper_hw_ret (uint64_t a)
{
env->pc = a & ~3;
env->ipr[IPR_EXC_ADDR] = a & 1;
env->intr_flag = 0;
/* XXX: re-enable interrupts and memory mapping */
}

19
target-alpha/translate.c
View File

@ -1301,6 +1301,19 @@ static void gen_cmp(TCGCond cond, int ra, int rb, int rc,
}
}
static void gen_rx(int ra, int set)
{
TCGv_i32 tmp;
if (ra != 31) {
tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUState, intr_flag));
}
tmp = tcg_const_i32(set);
tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUState, intr_flag));
tcg_temp_free_i32(tmp);
}
static inline int translate_one(DisasContext *ctx, uint32_t insn)
{
uint32_t palcode;
@ -2392,16 +2405,14 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0xE000:
/* RC */
if (ra != 31)
gen_helper_rc(cpu_ir[ra]);
gen_rx(ra, 0);
break;
case 0xE800:
/* ECB */
break;
case 0xF000:
/* RS */
if (ra != 31)
gen_helper_rs(cpu_ir[ra]);
gen_rx(ra, 1);
break;
case 0xF800:
/* WH64 */