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Merge remote-tracking branch 'afaerber/qom-cpu.v5' into staging

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* afaerber/qom-cpu.v5: (43 commits)
  qom: Introduce CPU class
  Rename CPUState -> CPUArchState
  xtensa hw/: Don't use CPUState
  sparc hw/: Don't use CPUState
  sh4 hw/: Don't use CPUState
  s390x hw/: Don't use CPUState
  ppc hw/: Don't use CPUState
  mips hw/: Don't use CPUState
  microblaze hw/: Don't use CPUState
  m68k hw/: Don't use CPUState
  lm32 hw/: Don't use CPUState
  i386 hw/: Don't use CPUState
  cris hw/: Don't use CPUState
  arm hw/: Don't use CPUState
  alpha hw/: Don't use CPUState
  xtensa-semi: Don't use CPUState
  m68k-semi: Don't use CPUState
  arm-semi: Don't use CPUState
  target-xtensa: Don't overuse CPUState
  target-unicore32: Don't overuse CPUState
  ...
This commit is contained in:
Anthony Liguori 2012-03-14 16:47:49 -05:00
commit aea6ff7fa0
229 changed files with 3142 additions and 2978 deletions
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3
Makefile.objs
View File

@ -14,6 +14,7 @@ universal-obj-y += $(qobject-obj-y)
# QOM
include $(SRC_PATH)/qom/Makefile
qom-obj-y = $(addprefix qom/, $(qom-y))
qom-obj-twice-y = $(addprefix qom/, $(qom-twice-y))
universal-obj-y += $(qom-obj-y)
@ -93,6 +94,7 @@ fsdev-obj-$(CONFIG_VIRTFS) += $(addprefix fsdev/, $(fsdev-nested-y))
common-obj-y = $(block-obj-y) blockdev.o
common-obj-y += $(net-obj-y)
common-obj-y += $(qom-obj-twice-y)
common-obj-$(CONFIG_LINUX) += $(fsdev-obj-$(CONFIG_LINUX))
common-obj-y += readline.o console.o cursor.o
common-obj-y += $(oslib-obj-y)
@ -200,6 +202,7 @@ user-obj-y += cutils.o cache-utils.o
user-obj-y += module.o
user-obj-y += qemu-user.o
user-obj-y += $(trace-obj-y)
user-obj-y += $(qom-obj-twice-y)
######################################################################
# libhw

10
arm-semi.c
View File

@ -108,7 +108,7 @@ static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code)
return code;
}
#else
static inline uint32_t set_swi_errno(CPUState *env, uint32_t code)
static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code)
{
return code;
}
@ -122,7 +122,7 @@ static target_ulong arm_semi_syscall_len;
static target_ulong syscall_err;
#endif
static void arm_semi_cb(CPUState *env, target_ulong ret, target_ulong err)
static void arm_semi_cb(CPUARMState *env, target_ulong ret, target_ulong err)
{
#ifdef CONFIG_USER_ONLY
TaskState *ts = env->opaque;
@ -152,7 +152,7 @@ static void arm_semi_cb(CPUState *env, target_ulong ret, target_ulong err)
}
}
static void arm_semi_flen_cb(CPUState *env, target_ulong ret, target_ulong err)
static void arm_semi_flen_cb(CPUARMState *env, target_ulong ret, target_ulong err)
{
/* The size is always stored in big-endian order, extract
the value. We assume the size always fit in 32 bits. */
@ -174,7 +174,7 @@ static void arm_semi_flen_cb(CPUState *env, target_ulong ret, target_ulong err)
__arg; \
})
#define SET_ARG(n, val) put_user_ual(val, args + (n) * 4)
uint32_t do_arm_semihosting(CPUState *env)
uint32_t do_arm_semihosting(CPUARMState *env)
{
target_ulong args;
char * s;
@ -184,7 +184,7 @@ uint32_t do_arm_semihosting(CPUState *env)
#ifdef CONFIG_USER_ONLY
TaskState *ts = env->opaque;
#else
CPUState *ts = env;
CPUARMState *ts = env;
#endif
nr = env->regs[0];

14
bsd-user/main.c
View File

@ -63,18 +63,18 @@ void gemu_log(const char *fmt, ...)
}
#if defined(TARGET_I386)
int cpu_get_pic_interrupt(CPUState *env)
int cpu_get_pic_interrupt(CPUX86State *env)
{
return -1;
}
#endif
/* These are no-ops because we are not threadsafe. */
static inline void cpu_exec_start(CPUState *env)
static inline void cpu_exec_start(CPUArchState *env)
{
}
static inline void cpu_exec_end(CPUState *env)
static inline void cpu_exec_end(CPUArchState *env)
{
}
@ -109,7 +109,7 @@ void cpu_list_unlock(void)
/***********************************************************/
/* CPUX86 core interface */
void cpu_smm_update(CPUState *env)
void cpu_smm_update(CPUX86State *env)
{
}
@ -713,7 +713,7 @@ static void usage(void)
exit(1);
}
THREAD CPUState *thread_env;
THREAD CPUArchState *thread_env;
/* Assumes contents are already zeroed. */
void init_task_state(TaskState *ts)
@ -737,7 +737,7 @@ int main(int argc, char **argv)
struct target_pt_regs regs1, *regs = &regs1;
struct image_info info1, *info = &info1;
TaskState ts1, *ts = &ts1;
CPUState *env;
CPUArchState *env;
int optind;
const char *r;
int gdbstub_port = 0;
@ -917,7 +917,7 @@ int main(int argc, char **argv)
exit(1);
}
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_reset(env);
cpu_state_reset(env);
#endif
thread_env = env;

12
bsd-user/qemu.h
View File

@ -139,8 +139,8 @@ abi_long do_openbsd_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg2, abi_long arg3, abi_long arg4,
abi_long arg5, abi_long arg6);
void gemu_log(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
extern THREAD CPUState *thread_env;
void cpu_loop(CPUState *env);
extern THREAD CPUArchState *thread_env;
void cpu_loop(CPUArchState *env);
char *target_strerror(int err);
int get_osversion(void);
void fork_start(void);
@ -167,13 +167,13 @@ void print_openbsd_syscall_ret(int num, abi_long ret);
extern int do_strace;
/* signal.c */
void process_pending_signals(CPUState *cpu_env);
void process_pending_signals(CPUArchState *cpu_env);
void signal_init(void);
//int queue_signal(CPUState *env, int sig, target_siginfo_t *info);
//int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info);
//void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info);
//void target_to_host_siginfo(siginfo_t *info, const target_siginfo_t *tinfo);
long do_sigreturn(CPUState *env);
long do_rt_sigreturn(CPUState *env);
long do_sigreturn(CPUArchState *env);
long do_rt_sigreturn(CPUArchState *env);
abi_long do_sigaltstack(abi_ulong uss_addr, abi_ulong uoss_addr, abi_ulong sp);
/* mmap.c */

2
bsd-user/signal.c
View File

@ -33,6 +33,6 @@ void signal_init(void)
{
}
void process_pending_signals(CPUState *cpu_env)
void process_pending_signals(CPUArchState *cpu_env)
{
}

1
configure vendored
View File

@ -3921,6 +3921,7 @@ fi
d=libuser
mkdir -p $d
mkdir -p $d/trace
mkdir -p $d/qom
symlink $source_path/Makefile.user $d/Makefile
if test "$docs" = "yes" ; then

56
cpu-all.h
View File

@ -322,20 +322,20 @@ void page_set_flags(target_ulong start, target_ulong end, int flags);
int page_check_range(target_ulong start, target_ulong len, int flags);
#endif
CPUState *cpu_copy(CPUState *env);
CPUState *qemu_get_cpu(int cpu);
CPUArchState *cpu_copy(CPUArchState *env);
CPUArchState *qemu_get_cpu(int cpu);
#define CPU_DUMP_CODE 0x00010000
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
int flags);
void cpu_dump_statistics(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
void cpu_dump_statistics(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
int flags);
void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...)
void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
extern CPUState *first_cpu;
DECLARE_TLS(CPUState *,cpu_single_env);
extern CPUArchState *first_cpu;
DECLARE_TLS(CPUArchState *,cpu_single_env);
#define cpu_single_env tls_var(cpu_single_env)
/* Flags for use in ENV->INTERRUPT_PENDING.
@ -389,23 +389,23 @@ DECLARE_TLS(CPUState *,cpu_single_env);
| CPU_INTERRUPT_TGT_EXT_4)
#ifndef CONFIG_USER_ONLY
typedef void (*CPUInterruptHandler)(CPUState *, int);
typedef void (*CPUInterruptHandler)(CPUArchState *, int);
extern CPUInterruptHandler cpu_interrupt_handler;
static inline void cpu_interrupt(CPUState *s, int mask)
static inline void cpu_interrupt(CPUArchState *s, int mask)
{
cpu_interrupt_handler(s, mask);
}
#else /* USER_ONLY */
void cpu_interrupt(CPUState *env, int mask);
void cpu_interrupt(CPUArchState *env, int mask);
#endif /* USER_ONLY */
void cpu_reset_interrupt(CPUState *env, int mask);
void cpu_reset_interrupt(CPUArchState *env, int mask);
void cpu_exit(CPUState *s);
void cpu_exit(CPUArchState *s);
bool qemu_cpu_has_work(CPUState *env);
bool qemu_cpu_has_work(CPUArchState *env);
/* Breakpoint/watchpoint flags */
#define BP_MEM_READ 0x01
@ -416,26 +416,26 @@ bool qemu_cpu_has_work(CPUState *env);
#define BP_GDB 0x10
#define BP_CPU 0x20
int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
CPUBreakpoint **breakpoint);
int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags);
void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint);
void cpu_breakpoint_remove_all(CPUState *env, int mask);
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
int flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUState *env, target_ulong addr,
int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
target_ulong len, int flags);
void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint);
void cpu_watchpoint_remove_all(CPUState *env, int mask);
void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
void cpu_single_step(CPUState *env, int enabled);
void cpu_reset(CPUState *s);
int cpu_is_stopped(CPUState *env);
void run_on_cpu(CPUState *env, void (*func)(void *data), void *data);
void cpu_single_step(CPUArchState *env, int enabled);
void cpu_state_reset(CPUArchState *s);
int cpu_is_stopped(CPUArchState *env);
void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data);
#define CPU_LOG_TB_OUT_ASM (1 << 0)
#define CPU_LOG_TB_IN_ASM (1 << 1)
@ -466,7 +466,7 @@ int cpu_str_to_log_mask(const char *str);
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
/* memory API */
@ -508,12 +508,12 @@ extern int mem_prealloc;
/* Set if TLB entry is an IO callback. */
#define TLB_MMIO (1 << 5)
void cpu_tlb_update_dirty(CPUState *env);
void cpu_tlb_update_dirty(CPUArchState *env);
void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
#endif /* !CONFIG_USER_ONLY */
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write);
#endif /* CPU_ALL_H */

2
cpu-defs.h
View File

@ -202,7 +202,7 @@ typedef struct CPUWatchpoint {
jmp_buf jmp_env; \
int exception_index; \
\
CPUState *next_cpu; /* next CPU sharing TB cache */ \
CPUArchState *next_cpu; /* next CPU sharing TB cache */ \
int cpu_index; /* CPU index (informative) */ \
uint32_t host_tid; /* host thread ID */ \
int numa_node; /* NUMA node this cpu is belonging to */ \

20
cpu-exec.c
View File

@ -26,12 +26,12 @@ int tb_invalidated_flag;
//#define CONFIG_DEBUG_EXEC
bool qemu_cpu_has_work(CPUState *env)
bool qemu_cpu_has_work(CPUArchState *env)
{
return cpu_has_work(env);
}
void cpu_loop_exit(CPUState *env)
void cpu_loop_exit(CPUArchState *env)
{
env->current_tb = NULL;
longjmp(env->jmp_env, 1);
@ -41,7 +41,7 @@ void cpu_loop_exit(CPUState *env)
restored in a state compatible with the CPU emulator
*/
#if defined(CONFIG_SOFTMMU)
void cpu_resume_from_signal(CPUState *env, void *puc)
void cpu_resume_from_signal(CPUArchState *env, void *puc)
{
/* XXX: restore cpu registers saved in host registers */
@ -52,7 +52,7 @@ void cpu_resume_from_signal(CPUState *env, void *puc)
/* Execute the code without caching the generated code. An interpreter
could be used if available. */
static void cpu_exec_nocache(CPUState *env, int max_cycles,
static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
TranslationBlock *orig_tb)
{
unsigned long next_tb;
@ -79,7 +79,7 @@ static void cpu_exec_nocache(CPUState *env, int max_cycles,
tb_free(tb);
}
static TranslationBlock *tb_find_slow(CPUState *env,
static TranslationBlock *tb_find_slow(CPUArchState *env,
target_ulong pc,
target_ulong cs_base,
uint64_t flags)
@ -135,7 +135,7 @@ static TranslationBlock *tb_find_slow(CPUState *env,
return tb;
}
static inline TranslationBlock *tb_find_fast(CPUState *env)
static inline TranslationBlock *tb_find_fast(CPUArchState *env)
{
TranslationBlock *tb;
target_ulong cs_base, pc;
@ -163,7 +163,7 @@ CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
return old_handler;
}
static void cpu_handle_debug_exception(CPUState *env)
static void cpu_handle_debug_exception(CPUArchState *env)
{
CPUWatchpoint *wp;
@ -181,7 +181,7 @@ static void cpu_handle_debug_exception(CPUState *env)
volatile sig_atomic_t exit_request;
int cpu_exec(CPUState *env)
int cpu_exec(CPUArchState *env)
{
int ret, interrupt_request;
TranslationBlock *tb;
@ -339,11 +339,9 @@ int cpu_exec(CPUState *env)
}
}
#elif defined(TARGET_PPC)
#if 0
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
cpu_reset(env);
cpu_state_reset(env);
}
#endif
if (interrupt_request & CPU_INTERRUPT_HARD) {
ppc_hw_interrupt(env);
if (env->pending_interrupts == 0)

76
cpus.c
View File

@ -58,7 +58,7 @@
#endif /* CONFIG_LINUX */
static CPUState *next_cpu;
static CPUArchState *next_cpu;
/***********************************************************/
/* guest cycle counter */
@ -89,7 +89,7 @@ TimersState timers_state;
int64_t cpu_get_icount(void)
{
int64_t icount;
CPUState *env = cpu_single_env;
CPUArchState *env = cpu_single_env;
icount = qemu_icount;
if (env) {
@ -339,7 +339,7 @@ void configure_icount(const char *option)
void hw_error(const char *fmt, ...)
{
va_list ap;
CPUState *env;
CPUArchState *env;
va_start(ap, fmt);
fprintf(stderr, "qemu: hardware error: ");
@ -359,7 +359,7 @@ void hw_error(const char *fmt, ...)
void cpu_synchronize_all_states(void)
{
CPUState *cpu;
CPUArchState *cpu;
for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) {
cpu_synchronize_state(cpu);
@ -368,7 +368,7 @@ void cpu_synchronize_all_states(void)
void cpu_synchronize_all_post_reset(void)
{
CPUState *cpu;
CPUArchState *cpu;
for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) {
cpu_synchronize_post_reset(cpu);
@ -377,14 +377,14 @@ void cpu_synchronize_all_post_reset(void)
void cpu_synchronize_all_post_init(void)
{
CPUState *cpu;
CPUArchState *cpu;
for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) {
cpu_synchronize_post_init(cpu);
}
}
int cpu_is_stopped(CPUState *env)
int cpu_is_stopped(CPUArchState *env)
{
return !runstate_is_running() || env->stopped;
}
@ -402,7 +402,7 @@ static void do_vm_stop(RunState state)
}
}
static int cpu_can_run(CPUState *env)
static int cpu_can_run(CPUArchState *env)
{
if (env->stop) {
return 0;
@ -413,7 +413,7 @@ static int cpu_can_run(CPUState *env)
return 1;
}
static bool cpu_thread_is_idle(CPUState *env)
static bool cpu_thread_is_idle(CPUArchState *env)
{
if (env->stop || env->queued_work_first) {
return false;
@ -430,7 +430,7 @@ static bool cpu_thread_is_idle(CPUState *env)
bool all_cpu_threads_idle(void)
{
CPUState *env;
CPUArchState *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (!cpu_thread_is_idle(env)) {
@ -440,7 +440,7 @@ bool all_cpu_threads_idle(void)
return true;
}
static void cpu_handle_guest_debug(CPUState *env)
static void cpu_handle_guest_debug(CPUArchState *env)
{
gdb_set_stop_cpu(env);
qemu_system_debug_request();
@ -494,7 +494,7 @@ static void qemu_init_sigbus(void)
prctl(PR_MCE_KILL, PR_MCE_KILL_SET, PR_MCE_KILL_EARLY, 0, 0);
}
static void qemu_kvm_eat_signals(CPUState *env)
static void qemu_kvm_eat_signals(CPUArchState *env)
{
struct timespec ts = { 0, 0 };
siginfo_t siginfo;
@ -537,7 +537,7 @@ static void qemu_init_sigbus(void)
{
}
static void qemu_kvm_eat_signals(CPUState *env)
static void qemu_kvm_eat_signals(CPUArchState *env)
{
}
#endif /* !CONFIG_LINUX */
@ -547,7 +547,7 @@ static void dummy_signal(int sig)
{
}
static void qemu_kvm_init_cpu_signals(CPUState *env)
static void qemu_kvm_init_cpu_signals(CPUArchState *env)
{
int r;
sigset_t set;
@ -582,7 +582,7 @@ static void qemu_tcg_init_cpu_signals(void)
}
#else /* _WIN32 */
static void qemu_kvm_init_cpu_signals(CPUState *env)
static void qemu_kvm_init_cpu_signals(CPUArchState *env)
{
abort();
}
@ -619,7 +619,7 @@ void qemu_init_cpu_loop(void)
qemu_thread_get_self(&io_thread);
}
void run_on_cpu(CPUState *env, void (*func)(void *data), void *data)
void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data)
{
struct qemu_work_item wi;
@ -641,14 +641,14 @@ void run_on_cpu(CPUState *env, void (*func)(void *data), void *data)
qemu_cpu_kick(env);
while (!wi.done) {
CPUState *self_env = cpu_single_env;
CPUArchState *self_env = cpu_single_env;
qemu_cond_wait(&qemu_work_cond, &qemu_global_mutex);
cpu_single_env = self_env;
}
}
static void flush_queued_work(CPUState *env)
static void flush_queued_work(CPUArchState *env)
{
struct qemu_work_item *wi;
@ -665,7 +665,7 @@ static void flush_queued_work(CPUState *env)
qemu_cond_broadcast(&qemu_work_cond);
}
static void qemu_wait_io_event_common(CPUState *env)
static void qemu_wait_io_event_common(CPUArchState *env)
{
if (env->stop) {
env->stop = 0;
@ -678,7 +678,7 @@ static void qemu_wait_io_event_common(CPUState *env)
static void qemu_tcg_wait_io_event(void)
{
CPUState *env;
CPUArchState *env;
while (all_cpu_threads_idle()) {
/* Start accounting real time to the virtual clock if the CPUs
@ -696,7 +696,7 @@ static void qemu_tcg_wait_io_event(void)
}
}
static void qemu_kvm_wait_io_event(CPUState *env)
static void qemu_kvm_wait_io_event(CPUArchState *env)
{
while (cpu_thread_is_idle(env)) {
qemu_cond_wait(env->halt_cond, &qemu_global_mutex);
@ -708,7 +708,7 @@ static void qemu_kvm_wait_io_event(CPUState *env)
static void *qemu_kvm_cpu_thread_fn(void *arg)
{
CPUState *env = arg;
CPUArchState *env = arg;
int r;
qemu_mutex_lock(&qemu_global_mutex);
@ -745,7 +745,7 @@ static void tcg_exec_all(void);
static void *qemu_tcg_cpu_thread_fn(void *arg)
{
CPUState *env = arg;
CPUArchState *env = arg;
qemu_tcg_init_cpu_signals();
qemu_thread_get_self(env->thread);
@ -779,7 +779,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg)
return NULL;
}
static void qemu_cpu_kick_thread(CPUState *env)
static void qemu_cpu_kick_thread(CPUArchState *env)
{
#ifndef _WIN32
int err;
@ -800,7 +800,7 @@ static void qemu_cpu_kick_thread(CPUState *env)
void qemu_cpu_kick(void *_env)
{
CPUState *env = _env;
CPUArchState *env = _env;
qemu_cond_broadcast(env->halt_cond);
if (kvm_enabled() && !env->thread_kicked) {
@ -825,7 +825,7 @@ void qemu_cpu_kick_self(void)
int qemu_cpu_is_self(void *_env)
{
CPUState *env = _env;
CPUArchState *env = _env;
return qemu_thread_is_self(env->thread);
}
@ -852,7 +852,7 @@ void qemu_mutex_unlock_iothread(void)
static int all_vcpus_paused(void)
{
CPUState *penv = first_cpu;
CPUArchState *penv = first_cpu;
while (penv) {
if (!penv->stopped) {
@ -866,7 +866,7 @@ static int all_vcpus_paused(void)
void pause_all_vcpus(void)
{
CPUState *penv = first_cpu;
CPUArchState *penv = first_cpu;
qemu_clock_enable(vm_clock, false);
while (penv) {
@ -899,7 +899,7 @@ void pause_all_vcpus(void)
void resume_all_vcpus(void)
{
CPUState *penv = first_cpu;
CPUArchState *penv = first_cpu;
qemu_clock_enable(vm_clock, true);
while (penv) {
@ -912,7 +912,7 @@ void resume_all_vcpus(void)
static void qemu_tcg_init_vcpu(void *_env)
{
CPUState *env = _env;
CPUArchState *env = _env;
/* share a single thread for all cpus with TCG */
if (!tcg_cpu_thread) {
@ -935,7 +935,7 @@ static void qemu_tcg_init_vcpu(void *_env)
}
}
static void qemu_kvm_start_vcpu(CPUState *env)
static void qemu_kvm_start_vcpu(CPUArchState *env)
{
env->thread = g_malloc0(sizeof(QemuThread));
env->halt_cond = g_malloc0(sizeof(QemuCond));
@ -949,7 +949,7 @@ static void qemu_kvm_start_vcpu(CPUState *env)
void qemu_init_vcpu(void *_env)
{
CPUState *env = _env;
CPUArchState *env = _env;
env->nr_cores = smp_cores;
env->nr_threads = smp_threads;
@ -996,7 +996,7 @@ void vm_stop_force_state(RunState state)
}
}
static int tcg_cpu_exec(CPUState *env)
static int tcg_cpu_exec(CPUArchState *env)
{
int ret;
#ifdef CONFIG_PROFILER
@ -1045,7 +1045,7 @@ static void tcg_exec_all(void)
next_cpu = first_cpu;
}
for (; next_cpu != NULL && !exit_request; next_cpu = next_cpu->next_cpu) {
CPUState *env = next_cpu;
CPUArchState *env = next_cpu;
qemu_clock_enable(vm_clock,
(env->singlestep_enabled & SSTEP_NOTIMER) == 0);
@ -1065,7 +1065,7 @@ static void tcg_exec_all(void)
void set_numa_modes(void)
{
CPUState *env;
CPUArchState *env;
int i;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
@ -1111,7 +1111,7 @@ void list_cpus(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
CpuInfoList *qmp_query_cpus(Error **errp)
{
CpuInfoList *head = NULL, *cur_item = NULL;
CPUState *env;
CPUArchState *env;
for(env = first_cpu; env != NULL; env = env->next_cpu) {
CpuInfoList *info;
@ -1157,7 +1157,7 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
{
FILE *f;
uint32_t l;
CPUState *env;
CPUArchState *env;
uint8_t buf[1024];
if (!has_cpu) {
@ -1232,7 +1232,7 @@ exit:
void qmp_inject_nmi(Error **errp)
{
#if defined(TARGET_I386)
CPUState *env;
CPUArchState *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (!env->apic_state) {

22
darwin-user/main.c
View File

@ -71,44 +71,44 @@ void gemu_log(const char *fmt, ...)
va_end(ap);
}
int cpu_get_pic_interrupt(CPUState *env)
int cpu_get_pic_interrupt(CPUArchState *env)
{
return -1;
}
#ifdef TARGET_PPC
static inline uint64_t cpu_ppc_get_tb (CPUState *env)
static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
{
/* TO FIX */
return 0;
}
uint64_t cpu_ppc_load_tbl (CPUState *env)
uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
{
return cpu_ppc_get_tb(env);
}
uint32_t cpu_ppc_load_tbu (CPUState *env)
uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
{
return cpu_ppc_get_tb(env) >> 32;
}
uint64_t cpu_ppc_load_atbl (CPUState *env)
uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
{
return cpu_ppc_get_tb(env);
}
uint32_t cpu_ppc_load_atbu (CPUState *env)
uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
{
return cpu_ppc_get_tb(env) >> 32;
}
uint32_t cpu_ppc601_load_rtcu (CPUState *env)
uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
{
cpu_ppc_load_tbu(env);
}
uint32_t cpu_ppc601_load_rtcl (CPUState *env)
uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
{
return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
}
@ -729,7 +729,7 @@ static void usage(void)
}
/* XXX: currently only used for async signals (see signal.c) */
CPUState *global_env;
CPUArchState *global_env;
/* used to free thread contexts */
TaskState *first_task_state;
@ -741,7 +741,7 @@ int main(int argc, char **argv)
const char *log_mask = NULL;
struct target_pt_regs regs1, *regs = &regs1;
TaskState ts1, *ts = &ts1;
CPUState *env;
CPUArchState *env;
int optind;
short use_gdbstub = 0;
const char *r;
@ -858,7 +858,7 @@ int main(int argc, char **argv)
/* NOTE: we need to init the CPU at this stage to get
qemu_host_page_size */
env = cpu_init(cpu_model);
cpu_reset(env);
cpu_state_reset(env);
printf("Starting %s with qemu\n----------------\n", filename);

6
darwin-user/qemu.h
View File

@ -104,8 +104,8 @@ void qerror(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
void write_dt(void *ptr, unsigned long addr, unsigned long limit, int flags);
extern CPUState *global_env;
void cpu_loop(CPUState *env);
extern CPUArchState *global_env;
void cpu_loop(CPUArchState *env);
void init_paths(const char *prefix);
const char *path(const char *pathname);
@ -122,7 +122,7 @@ void signal_init(void);
int queue_signal(int sig, target_siginfo_t *info);
void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info);
void target_to_host_siginfo(siginfo_t *info, const target_siginfo_t *tinfo);
long do_sigreturn(CPUState *env, int num);
long do_sigreturn(CPUArchState *env, int num);
/* machload.c */
int mach_exec(const char * filename, char ** argv, char ** envp,

8
darwin-user/signal.c
View File

@ -315,7 +315,7 @@ get_sigframe(struct emulated_sigaction *ka, CPUX86State *env, size_t frame_size)
}
static void setup_frame(int sig, struct emulated_sigaction *ka,
void *set, CPUState *env)
void *set, CPUX86State *env)
{
void *frame;
@ -336,7 +336,7 @@ give_sigsegv:
force_sig(SIGSEGV /* , current */);
}
long do_sigreturn(CPUState *env, int num)
long do_sigreturn(CPUX86State *env, int num)
{
int i = 0;
struct target_sigcontext *scp = get_int_arg(&i, env);
@ -377,12 +377,12 @@ long do_sigreturn(CPUState *env, int num)
#else
static void setup_frame(int sig, struct emulated_sigaction *ka,
void *set, CPUState *env)
void *set, CPUArchState *env)
{
fprintf(stderr, "setup_frame: not implemented\n");
}
long do_sigreturn(CPUState *env, int num)
long do_sigreturn(CPUArchState *env, int num)
{
int i = 0;
struct target_sigcontext *scp = get_int_arg(&i, env);

2
def-helper.h
View File

@ -52,7 +52,7 @@
#define dh_ctype_tl target_ulong
#define dh_ctype_ptr void *
#define dh_ctype_void void
#define dh_ctype_env CPUState *
#define dh_ctype_env CPUArchState *
#define dh_ctype(t) dh_ctype_##t
/* We can't use glue() here because it falls foul of C preprocessor

4
disas.c
View File

@ -339,7 +339,7 @@ const char *lookup_symbol(target_ulong orig_addr)
#include "monitor.h"
static int monitor_disas_is_physical;
static CPUState *monitor_disas_env;
static CPUArchState *monitor_disas_env;
static int
monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
@ -363,7 +363,7 @@ monitor_fprintf(FILE *stream, const char *fmt, ...)
return 0;
}
void monitor_disas(Monitor *mon, CPUState *env,
void monitor_disas(Monitor *mon, CPUArchState *env,
target_ulong pc, int nb_insn, int is_physical, int flags)
{
int count, i;

2
disas.h
View File

@ -8,7 +8,7 @@
void disas(FILE *out, void *code, unsigned long size);
void target_disas(FILE *out, target_ulong code, target_ulong size, int flags);
void monitor_disas(Monitor *mon, CPUState *env,
void monitor_disas(Monitor *mon, CPUArchState *env,
target_ulong pc, int nb_insn, int is_physical, int flags);
/* Look up symbol for debugging purpose. Returns "" if unknown. */

4
dyngen-exec.h
View File

@ -61,10 +61,10 @@
#endif
#if defined(AREG0)
register CPUState *env asm(AREG0);
register CPUArchState *env asm(AREG0);
#else
/* TODO: Try env = cpu_single_env. */
extern CPUState *env;
extern CPUArchState *env;
#endif
#endif /* !defined(__DYNGEN_EXEC_H__) */

38
exec-all.h
View File

@ -76,30 +76,30 @@ extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
#include "qemu-log.h"
void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb,
void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
int pc_pos);
void cpu_gen_init(void);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb,
CPUState *env, unsigned long searched_pc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_io_recompile(CPUState *env, void *retaddr);
TranslationBlock *tb_gen_code(CPUState *env,
CPUArchState *env, unsigned long searched_pc);
void cpu_resume_from_signal(CPUArchState *env1, void *puc);
void cpu_io_recompile(CPUArchState *env, void *retaddr);
TranslationBlock *tb_gen_code(CPUArchState *env,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
void cpu_exec_init(CPUState *env);
void QEMU_NORETURN cpu_loop_exit(CPUState *env1);
void cpu_exec_init(CPUArchState *env);
void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
#if !defined(CONFIG_USER_ONLY)
void tlb_set_page(CPUState *env, target_ulong vaddr,
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
target_phys_addr_t paddr, int prot,
int mmu_idx, target_ulong size);
#endif
@ -182,7 +182,7 @@ static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
}
void tb_free(TranslationBlock *tb);
void tb_flush(CPUState *env);
void tb_flush(CPUArchState *env);
void tb_link_page(TranslationBlock *tb,
tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
@ -305,7 +305,7 @@ uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
uint64_t value, unsigned size);
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr);
#include "softmmu_defs.h"
@ -333,15 +333,15 @@ void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
#endif
#if defined(CONFIG_USER_ONLY)
static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
{
return addr;
}
#else
tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr);
tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
#endif
typedef void (CPUDebugExcpHandler)(CPUState *env);
typedef void (CPUDebugExcpHandler)(CPUArchState *env);
CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
@ -353,7 +353,7 @@ extern volatile sig_atomic_t exit_request;
/* Deterministic execution requires that IO only be performed on the last
instruction of a TB so that interrupts take effect immediately. */
static inline int can_do_io(CPUState *env)
static inline int can_do_io(CPUArchState *env)
{
if (!use_icount) {
return 1;

114
exec.c
View File

@ -123,10 +123,10 @@ static MemoryRegion io_mem_subpage_ram;
#endif
CPUState *first_cpu;
CPUArchState *first_cpu;
/* current CPU in the current thread. It is only valid inside
cpu_exec() */
DEFINE_TLS(CPUState *,cpu_single_env);
DEFINE_TLS(CPUArchState *,cpu_single_env);
/* 0 = Do not count executed instructions.
1 = Precise instruction counting.
2 = Adaptive rate instruction counting. */
@ -509,7 +509,7 @@ static target_phys_addr_t section_addr(MemoryRegionSection *section,
}
static void tlb_protect_code(ram_addr_t ram_addr);
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
static void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
target_ulong vaddr);
#define mmap_lock() do { } while(0)
#define mmap_unlock() do { } while(0)
@ -661,7 +661,7 @@ void cpu_exec_init_all(void)
static int cpu_common_post_load(void *opaque, int version_id)
{
CPUState *env = opaque;
CPUArchState *env = opaque;
/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
version_id is increased. */
@ -678,16 +678,16 @@ static const VMStateDescription vmstate_cpu_common = {
.minimum_version_id_old = 1,
.post_load = cpu_common_post_load,
.fields = (VMStateField []) {
VMSTATE_UINT32(halted, CPUState),
VMSTATE_UINT32(interrupt_request, CPUState),
VMSTATE_UINT32(halted, CPUArchState),
VMSTATE_UINT32(interrupt_request, CPUArchState),
VMSTATE_END_OF_LIST()
}
};
#endif
CPUState *qemu_get_cpu(int cpu)
CPUArchState *qemu_get_cpu(int cpu)
{
CPUState *env = first_cpu;
CPUArchState *env = first_cpu;
while (env) {
if (env->cpu_index == cpu)
@ -698,9 +698,9 @@ CPUState *qemu_get_cpu(int cpu)
return env;
}
void cpu_exec_init(CPUState *env)
void cpu_exec_init(CPUArchState *env)
{
CPUState **penv;
CPUArchState **penv;
int cpu_index;
#if defined(CONFIG_USER_ONLY)
@ -799,9 +799,9 @@ static void page_flush_tb(void)
/* flush all the translation blocks */
/* XXX: tb_flush is currently not thread safe */
void tb_flush(CPUState *env1)
void tb_flush(CPUArchState *env1)
{
CPUState *env;
CPUArchState *env;
#if defined(DEBUG_FLUSH)
printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
(unsigned long)(code_gen_ptr - code_gen_buffer),
@ -934,7 +934,7 @@ static inline void tb_reset_jump(TranslationBlock *tb, int n)
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
{
CPUState *env;
CPUArchState *env;
PageDesc *p;
unsigned int h, n1;
tb_page_addr_t phys_pc;
@ -1043,7 +1043,7 @@ static void build_page_bitmap(PageDesc *p)
}
}
TranslationBlock *tb_gen_code(CPUState *env,
TranslationBlock *tb_gen_code(CPUArchState *env,
target_ulong pc, target_ulong cs_base,
int flags, int cflags)
{
@ -1090,7 +1090,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access)
{
TranslationBlock *tb, *tb_next, *saved_tb;
CPUState *env = cpu_single_env;
CPUArchState *env = cpu_single_env;
tb_page_addr_t tb_start, tb_end;
PageDesc *p;
int n;
@ -1227,7 +1227,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
int n;
#ifdef TARGET_HAS_PRECISE_SMC
TranslationBlock *current_tb = NULL;
CPUState *env = cpu_single_env;
CPUArchState *env = cpu_single_env;
int current_tb_modified = 0;
target_ulong current_pc = 0;
target_ulong current_cs_base = 0;
@ -1457,12 +1457,12 @@ static void tb_reset_jump_recursive(TranslationBlock *tb)
#if defined(TARGET_HAS_ICE)
#if defined(CONFIG_USER_ONLY)
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
{
tb_invalidate_phys_page_range(pc, pc + 1, 0);
}
#else
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
{
target_phys_addr_t addr;
ram_addr_t ram_addr;
@ -1482,19 +1482,19 @@ static void breakpoint_invalidate(CPUState *env, target_ulong pc)
#endif /* TARGET_HAS_ICE */
#if defined(CONFIG_USER_ONLY)
void cpu_watchpoint_remove_all(CPUState *env, int mask)
void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
{
}
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
int flags, CPUWatchpoint **watchpoint)
{
return -ENOSYS;
}
#else
/* Add a watchpoint. */
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
int flags, CPUWatchpoint **watchpoint)
{
target_ulong len_mask = ~(len - 1);
@ -1527,7 +1527,7 @@ int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
}
/* Remove a specific watchpoint. */
int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len,
int flags)
{
target_ulong len_mask = ~(len - 1);
@ -1544,7 +1544,7 @@ int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
}
/* Remove a specific watchpoint by reference. */
void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
{
QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
@ -1554,7 +1554,7 @@ void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
}
/* Remove all matching watchpoints. */
void cpu_watchpoint_remove_all(CPUState *env, int mask)
void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
{
CPUWatchpoint *wp, *next;
@ -1566,7 +1566,7 @@ void cpu_watchpoint_remove_all(CPUState *env, int mask)
#endif
/* Add a breakpoint. */
int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
CPUBreakpoint **breakpoint)
{
#if defined(TARGET_HAS_ICE)
@ -1594,7 +1594,7 @@ int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
}
/* Remove a specific breakpoint. */
int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
{
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
@ -1612,7 +1612,7 @@ int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
}
/* Remove a specific breakpoint by reference. */
void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
{
#if defined(TARGET_HAS_ICE)
QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
@ -1624,7 +1624,7 @@ void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
}
/* Remove all matching breakpoints. */
void cpu_breakpoint_remove_all(CPUState *env, int mask)
void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
{
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp, *next;
@ -1638,7 +1638,7 @@ void cpu_breakpoint_remove_all(CPUState *env, int mask)
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
void cpu_single_step(CPUState *env, int enabled)
void cpu_single_step(CPUArchState *env, int enabled)
{
#if defined(TARGET_HAS_ICE)
if (env->singlestep_enabled != enabled) {
@ -1694,7 +1694,7 @@ void cpu_set_log_filename(const char *filename)
cpu_set_log(loglevel);
}
static void cpu_unlink_tb(CPUState *env)
static void cpu_unlink_tb(CPUArchState *env)
{
/* FIXME: TB unchaining isn't SMP safe. For now just ignore the
problem and hope the cpu will stop of its own accord. For userspace
@ -1716,7 +1716,7 @@ static void cpu_unlink_tb(CPUState *env)
#ifndef CONFIG_USER_ONLY
/* mask must never be zero, except for A20 change call */
static void tcg_handle_interrupt(CPUState *env, int mask)
static void tcg_handle_interrupt(CPUArchState *env, int mask)
{
int old_mask;
@ -1747,19 +1747,19 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt;
#else /* CONFIG_USER_ONLY */
void cpu_interrupt(CPUState *env, int mask)
void cpu_interrupt(CPUArchState *env, int mask)
{
env->interrupt_request |= mask;
cpu_unlink_tb(env);
}
#endif /* CONFIG_USER_ONLY */
void cpu_reset_interrupt(CPUState *env, int mask)
void cpu_reset_interrupt(CPUArchState *env, int mask)
{
env->interrupt_request &= ~mask;
}
void cpu_exit(CPUState *env)
void cpu_exit(CPUArchState *env)
{
env->exit_request = 1;
cpu_unlink_tb(env);
@ -1837,7 +1837,7 @@ int cpu_str_to_log_mask(const char *str)
return mask;
}
void cpu_abort(CPUState *env, const char *fmt, ...)
void cpu_abort(CPUArchState *env, const char *fmt, ...)
{
va_list ap;
va_list ap2;
@ -1877,17 +1877,17 @@ void cpu_abort(CPUState *env, const char *fmt, ...)
abort();
}
CPUState *cpu_copy(CPUState *env)
CPUArchState *cpu_copy(CPUArchState *env)
{
CPUState *new_env = cpu_init(env->cpu_model_str);
CPUState *next_cpu = new_env->next_cpu;
CPUArchState *new_env = cpu_init(env->cpu_model_str);
CPUArchState *next_cpu = new_env->next_cpu;
int cpu_index = new_env->cpu_index;
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
CPUWatchpoint *wp;
#endif
memcpy(new_env, env, sizeof(CPUState));
memcpy(new_env, env, sizeof(CPUArchState));
/* Preserve chaining and index. */
new_env->next_cpu = next_cpu;
@ -1913,7 +1913,7 @@ CPUState *cpu_copy(CPUState *env)
#if !defined(CONFIG_USER_ONLY)
static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
static inline void tlb_flush_jmp_cache(CPUArchState *env, target_ulong addr)
{
unsigned int i;
@ -1947,7 +1947,7 @@ static CPUTLBEntry s_cputlb_empty_entry = {
* entries from the TLB at any time, so flushing more entries than
* required is only an efficiency issue, not a correctness issue.
*/
void tlb_flush(CPUState *env, int flush_global)
void tlb_flush(CPUArchState *env, int flush_global)
{
int i;
@ -1984,7 +1984,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
}
}
void tlb_flush_page(CPUState *env, target_ulong addr)
void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
int i;
int mmu_idx;
@ -2025,7 +2025,7 @@ static void tlb_protect_code(ram_addr_t ram_addr)
/* update the TLB so that writes in physical page 'phys_addr' are no longer
tested for self modifying code */
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
static void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
target_ulong vaddr)
{
cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
@ -2047,7 +2047,7 @@ static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
int dirty_flags)
{
CPUState *env;
CPUArchState *env;
unsigned long length, start1;
int i;
@ -2102,7 +2102,7 @@ static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
}
/* update the TLB according to the current state of the dirty bits */
void cpu_tlb_update_dirty(CPUState *env)
void cpu_tlb_update_dirty(CPUArchState *env)
{
int i;
int mmu_idx;
@ -2120,7 +2120,7 @@ static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
/* update the TLB corresponding to virtual page vaddr
so that it is no longer dirty */
static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
static inline void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
{
int i;
int mmu_idx;
@ -2133,7 +2133,7 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
/* Our TLB does not support large pages, so remember the area covered by
large pages and trigger a full TLB flush if these are invalidated. */
static void tlb_add_large_page(CPUState *env, target_ulong vaddr,
static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
target_ulong size)
{
target_ulong mask = ~(size - 1);
@ -2174,7 +2174,7 @@ static bool is_ram_rom_romd(MemoryRegionSection *s)
/* Add a new TLB entry. At most one entry for a given virtual address
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
void tlb_set_page(CPUState *env, target_ulong vaddr,
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
target_phys_addr_t paddr, int prot,
int mmu_idx, target_ulong size)
{
@ -2277,11 +2277,11 @@ void tlb_set_page(CPUState *env, target_ulong vaddr,
#else
void tlb_flush(CPUState *env, int flush_global)
void tlb_flush(CPUArchState *env, int flush_global)
{
}
void tlb_flush_page(CPUState *env, target_ulong addr)
void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
}
@ -2542,7 +2542,7 @@ int page_unprotect(target_ulong address, unsigned long pc, void *puc)
return 0;
}
static inline void tlb_set_dirty(CPUState *env,
static inline void tlb_set_dirty(CPUArchState *env,
unsigned long addr, target_ulong vaddr)
{
}
@ -3299,7 +3299,7 @@ static const MemoryRegionOps notdirty_mem_ops = {
/* Generate a debug exception if a watchpoint has been hit. */
static void check_watchpoint(int offset, int len_mask, int flags)
{
CPUState *env = cpu_single_env;
CPUArchState *env = cpu_single_env;
target_ulong pc, cs_base;
TranslationBlock *tb;
target_ulong vaddr;
@ -3544,7 +3544,7 @@ static void core_begin(MemoryListener *listener)
static void core_commit(MemoryListener *listener)
{
CPUState *env;
CPUArchState *env;
/* since each CPU stores ram addresses in its TLB cache, we must
reset the modified entries */
@ -3734,7 +3734,7 @@ MemoryRegion *get_system_io(void)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l, flags;
@ -4440,7 +4440,7 @@ void stq_be_phys(target_phys_addr_t addr, uint64_t val)
}
/* virtual memory access for debug (includes writing to ROM) */
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
@ -4471,7 +4471,7 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
/* in deterministic execution mode, instructions doing device I/Os
must be at the end of the TB */
void cpu_io_recompile(CPUState *env, void *retaddr)
void cpu_io_recompile(CPUArchState *env, void *retaddr)
{
TranslationBlock *tb;
uint32_t n, cflags;
@ -4585,7 +4585,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
is the offset relative to phys_ram_base */
tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
{
int mmu_idx, page_index, pd;
void *p;

100
gdbstub.c
View File

@ -42,7 +42,7 @@
#include "kvm.h"
#ifndef TARGET_CPU_MEMORY_RW_DEBUG
static inline int target_memory_rw_debug(CPUState *env, target_ulong addr,
static inline int target_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
return cpu_memory_rw_debug(env, addr, buf, len, is_write);
@ -287,9 +287,9 @@ enum RSState {
RS_SYSCALL,
};
typedef struct GDBState {
CPUState *c_cpu; /* current CPU for step/continue ops */
CPUState *g_cpu; /* current CPU for other ops */
CPUState *query_cpu; /* for q{f|s}ThreadInfo */
CPUArchState *c_cpu; /* current CPU for step/continue ops */
CPUArchState *g_cpu; /* current CPU for other ops */
CPUArchState *query_cpu; /* for q{f|s}ThreadInfo */
enum RSState state; /* parsing state */
char line_buf[MAX_PACKET_LENGTH];
int line_buf_index;
@ -533,7 +533,7 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
#define IDX_XMM_REGS (IDX_FP_REGS + 16)
#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
if (n < CPU_NB_REGS) {
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
@ -590,7 +590,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
{
uint16_t selector = ldl_p(mem_buf);
@ -615,7 +615,7 @@ static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
return 4;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@ -703,7 +703,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define GDB_CORE_XML "power-core.xml"
#endif
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
/* gprs */
@ -740,7 +740,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
/* gprs */
@ -801,7 +801,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define GET_REGA(val) GET_REGL(val)
#endif
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* g0..g7 */
@ -860,7 +860,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
{
#if defined(TARGET_ABI32)
abi_ulong tmp;
@ -944,7 +944,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 26
#define GDB_CORE_XML "arm-core.xml"
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
{
if (n < 16) {
/* Core integer register. */
@ -971,7 +971,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@ -1014,7 +1014,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define GDB_CORE_XML "cf-core.xml"
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* D0-D7 */
@ -1033,7 +1033,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@ -1058,7 +1058,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 73
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REGL(env->active_tc.gpr[n]);
@ -1104,7 +1104,7 @@ static unsigned int ieee_rm[] =
#define RESTORE_ROUNDING_MODE \
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
target_ulong tmp;
@ -1163,7 +1163,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 59
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
@ -1197,7 +1197,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@ -1244,7 +1244,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS (32 + 5)
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->regs[n]);
@ -1254,7 +1254,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@ -1275,7 +1275,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 49
static int
read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
{
if (n < 15) {
GET_REG32(env->regs[n]);
@ -1307,7 +1307,7 @@ read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
{
uint8_t srs;
@ -1337,7 +1337,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@ -1370,7 +1370,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 67
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
{
uint64_t val;
CPU_DoubleU d;
@ -1404,7 +1404,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
GET_REGL(val);
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
{
target_ulong tmp = ldtul_p(mem_buf);
CPU_DoubleU d;
@ -1440,7 +1440,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS S390_NUM_TOTAL_REGS
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
{
switch (n) {
case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
@ -1464,7 +1464,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
{
target_ulong tmpl;
uint32_t tmp32;
@ -1494,7 +1494,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#include "hw/lm32_pic.h"
#define NUM_CORE_REGS (32 + 7)
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->regs[n]);
@ -1527,7 +1527,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@ -1573,7 +1573,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
#define num_g_regs NUM_CORE_REGS
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
{
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
@ -1610,7 +1610,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
}
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
@ -1655,12 +1655,12 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 0
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
{
return 0;
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
{
return 0;
}
@ -1736,7 +1736,7 @@ static const char *get_feature_xml(const char *p, const char **newp)
}
#endif
static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
static int gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int reg)
{
GDBRegisterState *r;
@ -1751,7 +1751,7 @@ static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
return 0;
}
static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
static int gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int reg)
{
GDBRegisterState *r;
@ -1773,7 +1773,7 @@ static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
*/
void gdb_register_coprocessor(CPUState * env,
void gdb_register_coprocessor(CPUArchState * env,
gdb_reg_cb get_reg, gdb_reg_cb set_reg,
int num_regs, const char *xml, int g_pos)
{
@ -1820,7 +1820,7 @@ static const int xlat_gdb_type[] = {
static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
{
CPUState *env;
CPUArchState *env;
int err = 0;
if (kvm_enabled())
@ -1854,7 +1854,7 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
{
CPUState *env;
CPUArchState *env;
int err = 0;
if (kvm_enabled())
@ -1887,7 +1887,7 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
static void gdb_breakpoint_remove_all(void)
{
CPUState *env;
CPUArchState *env;
if (kvm_enabled()) {
kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
@ -1939,7 +1939,7 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
#endif
}
static inline int gdb_id(CPUState *env)
static inline int gdb_id(CPUArchState *env)
{
#if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
return env->host_tid;
@ -1948,9 +1948,9 @@ static inline int gdb_id(CPUState *env)
#endif
}
static CPUState *find_cpu(uint32_t thread_id)
static CPUArchState *find_cpu(uint32_t thread_id)
{
CPUState *env;
CPUArchState *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (gdb_id(env) == thread_id) {
@ -1963,7 +1963,7 @@ static CPUState *find_cpu(uint32_t thread_id)
static int gdb_handle_packet(GDBState *s, const char *line_buf)
{
CPUState *env;
CPUArchState *env;
const char *p;
uint32_t thread;
int ch, reg_size, type, res;
@ -2383,7 +2383,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
return RS_IDLE;
}
void gdb_set_stop_cpu(CPUState *env)
void gdb_set_stop_cpu(CPUArchState *env)
{
gdbserver_state->c_cpu = env;
gdbserver_state->g_cpu = env;
@ -2393,7 +2393,7 @@ void gdb_set_stop_cpu(CPUState *env)
static void gdb_vm_state_change(void *opaque, int running, RunState state)
{
GDBState *s = gdbserver_state;
CPUState *env = s->c_cpu;
CPUArchState *env = s->c_cpu;
char buf[256];
const char *type;
int ret;
@ -2602,7 +2602,7 @@ static void gdb_read_byte(GDBState *s, int ch)
}
/* Tell the remote gdb that the process has exited. */
void gdb_exit(CPUState *env, int code)
void gdb_exit(CPUArchState *env, int code)
{
GDBState *s;
char buf[4];
@ -2642,7 +2642,7 @@ gdb_queuesig (void)
}
int
gdb_handlesig (CPUState *env, int sig)
gdb_handlesig (CPUArchState *env, int sig)
{
GDBState *s;
char buf[256];
@ -2691,7 +2691,7 @@ gdb_handlesig (CPUState *env, int sig)
}
/* Tell the remote gdb that the process has exited due to SIG. */
void gdb_signalled(CPUState *env, int sig)
void gdb_signalled(CPUArchState *env, int sig)
{
GDBState *s;
char buf[4];
@ -2787,7 +2787,7 @@ int gdbserver_start(int port)
}
/* Disable gdb stub for child processes. */
void gdbserver_fork(CPUState *env)
void gdbserver_fork(CPUArchState *env)
{
GDBState *s = gdbserver_state;
if (gdbserver_fd < 0 || s->fd < 0)

16
gdbstub.h
View File

@ -11,22 +11,22 @@
#define GDB_WATCHPOINT_ACCESS 4
#ifdef NEED_CPU_H
typedef void (*gdb_syscall_complete_cb)(CPUState *env,
typedef void (*gdb_syscall_complete_cb)(CPUArchState *env,
target_ulong ret, target_ulong err);
void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...);
int use_gdb_syscalls(void);
void gdb_set_stop_cpu(CPUState *env);
void gdb_exit(CPUState *, int);
void gdb_set_stop_cpu(CPUArchState *env);
void gdb_exit(CPUArchState *, int);
#ifdef CONFIG_USER_ONLY
int gdb_queuesig (void);
int gdb_handlesig (CPUState *, int);
void gdb_signalled(CPUState *, int);
void gdbserver_fork(CPUState *);
int gdb_handlesig (CPUArchState *, int);
void gdb_signalled(CPUArchState *, int);
void gdbserver_fork(CPUArchState *);
#endif
/* Get or set a register. Returns the size of the register. */
typedef int (*gdb_reg_cb)(CPUState *env, uint8_t *buf, int reg);
void gdb_register_coprocessor(CPUState *env,
typedef int (*gdb_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);
void gdb_register_coprocessor(CPUArchState *env,
gdb_reg_cb get_reg, gdb_reg_cb set_reg,
int num_regs, const char *xml, int g_pos);

8
gen-icount.h
View File

@ -14,13 +14,13 @@ static inline void gen_icount_start(void)
icount_label = gen_new_label();
count = tcg_temp_local_new_i32();
tcg_gen_ld_i32(count, cpu_env, offsetof(CPUState, icount_decr.u32));
tcg_gen_ld_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u32));
/* This is a horrid hack to allow fixing up the value later. */
icount_arg = gen_opparam_ptr + 1;
tcg_gen_subi_i32(count, count, 0xdeadbeef);
tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label);
tcg_gen_st16_i32(count, cpu_env, offsetof(CPUState, icount_decr.u16.low));
tcg_gen_st16_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u16.low));
tcg_temp_free_i32(count);
}
@ -36,13 +36,13 @@ static void gen_icount_end(TranslationBlock *tb, int num_insns)
static inline void gen_io_start(void)
{
TCGv_i32 tmp = tcg_const_i32(1);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io));
tcg_temp_free_i32(tmp);
}
static inline void gen_io_end(void)
{
TCGv_i32 tmp = tcg_const_i32(0);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io));
tcg_temp_free_i32(tmp);
}

2
hw/alpha_dp264.c
View File

@ -49,7 +49,7 @@ static void clipper_init(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *cpus[4];
CPUAlphaState *cpus[4];
PCIBus *pci_bus;
ISABus *isa_bus;
qemu_irq rtc_irq;

2
hw/alpha_sys.h
View File

@ -11,7 +11,7 @@
#include "irq.h"
PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUState *[4],
PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUAlphaState *[4],
pci_map_irq_fn);
/* alpha_pci.c. */

14
hw/alpha_typhoon.c
View File

@ -21,7 +21,7 @@ typedef struct TyphoonCchip {
uint64_t drir;
uint64_t dim[4];
uint32_t iic[4];
CPUState *cpu[4];
CPUAlphaState *cpu[4];
} TyphoonCchip;
typedef struct TyphoonWindow {
@ -52,7 +52,7 @@ typedef struct TyphoonState {
} TyphoonState;
/* Called when one of DRIR or DIM changes. */
static void cpu_irq_change(CPUState *env, uint64_t req)
static void cpu_irq_change(CPUAlphaState *env, uint64_t req)
{
/* If there are any non-masked interrupts, tell the cpu. */
if (env) {
@ -66,7 +66,7 @@ static void cpu_irq_change(CPUState *env, uint64_t req)
static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
CPUState *env = cpu_single_env;
CPUAlphaState *env = cpu_single_env;
TyphoonState *s = opaque;
uint64_t ret = 0;
@ -347,7 +347,7 @@ static void cchip_write(void *opaque, target_phys_addr_t addr,
if ((newval ^ oldval) & 0xff0) {
int i;
for (i = 0; i < 4; ++i) {
CPUState *env = s->cchip.cpu[i];
CPUAlphaState *env = s->cchip.cpu[i];
if (env) {
/* IPI can be either cleared or set by the write. */
if (newval & (1 << (i + 8))) {
@ -655,7 +655,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level)
/* Deliver the interrupt to each CPU, considering each CPU's IIC. */
for (i = 0; i < 4; ++i) {
CPUState *env = s->cchip.cpu[i];
CPUAlphaState *env = s->cchip.cpu[i];
if (env) {
uint32_t iic = s->cchip.iic[i];
@ -693,7 +693,7 @@ static void typhoon_alarm_timer(void *opaque)
PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
qemu_irq *p_rtc_irq,
CPUState *cpus[4], pci_map_irq_fn sys_map_irq)
CPUAlphaState *cpus[4], pci_map_irq_fn sys_map_irq)
{
const uint64_t MB = 1024 * 1024;
const uint64_t GB = 1024 * MB;
@ -713,7 +713,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* Remember the CPUs so that we can deliver interrupts to them. */
for (i = 0; i < 4; i++) {
CPUState *env = cpus[i];
CPUAlphaState *env = cpus[i];
s->cchip.cpu[i] = env;
if (env) {
env->alarm_timer = qemu_new_timer_ns(rtc_clock,

2
hw/an5206.c
View File

@ -24,7 +24,7 @@ static void an5206_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;

2
hw/apic.h
View File

@ -22,7 +22,7 @@ void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
TPRAccess access);
/* pc.c */
int cpu_is_bsp(CPUState *env);
int cpu_is_bsp(CPUX86State *env);
DeviceState *cpu_get_current_apic(void);
#endif

8
hw/arm-misc.h
View File

@ -16,7 +16,7 @@
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(CPUState *env);
qemu_irq *arm_pic_init_cpu(CPUARMState *env);
/* armv7m.c */
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
@ -50,16 +50,16 @@ struct arm_boot_info {
* perform any necessary CPU reset handling and set the PC for thei
* secondary CPUs to point at this boot blob.
*/
void (*write_secondary_boot)(CPUState *env,
void (*write_secondary_boot)(CPUARMState *env,
const struct arm_boot_info *info);
void (*secondary_cpu_reset_hook)(CPUState *env,
void (*secondary_cpu_reset_hook)(CPUARMState *env,
const struct arm_boot_info *info);
/* Used internally by arm_boot.c */
int is_linux;
target_phys_addr_t initrd_size;
target_phys_addr_t entry;
};
void arm_load_kernel(CPUState *env, struct arm_boot_info *info);
void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info);
/* Multiplication factor to convert from system clock ticks to qemu timer
ticks. */

10
hw/arm_boot.c
View File

@ -59,7 +59,7 @@ static uint32_t smpboot[] = {
0 /* bootreg: Boot register address is held here */
};
static void default_write_secondary(CPUState *env,
static void default_write_secondary(CPUARMState *env,
const struct arm_boot_info *info)
{
int n;
@ -72,7 +72,7 @@ static void default_write_secondary(CPUState *env,
info->smp_loader_start);
}
static void default_reset_secondary(CPUState *env,
static void default_reset_secondary(CPUARMState *env,
const struct arm_boot_info *info)
{
stl_phys_notdirty(info->smp_bootreg_addr, 0);
@ -274,10 +274,10 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
static void do_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUARMState *env = opaque;
const struct arm_boot_info *info = env->boot_info;
cpu_reset(env);
cpu_state_reset(env);
if (info) {
if (!info->is_linux) {
/* Jump to the entry point. */
@ -300,7 +300,7 @@ static void do_cpu_reset(void *opaque)
}
}
void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
{
int kernel_size;
int initrd_size;

4
hw/arm_pic.c
View File

@ -13,7 +13,7 @@
/* Input 0 is IRQ and input 1 is FIQ. */
static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
CPUState *env = (CPUState *)opaque;
CPUARMState *env = (CPUARMState *)opaque;
switch (irq) {
case ARM_PIC_CPU_IRQ:
if (level)
@ -32,7 +32,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
}
}
qemu_irq *arm_pic_init_cpu(CPUState *env)
qemu_irq *arm_pic_init_cpu(CPUARMState *env)
{
return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2);
}

4
hw/armv7m.c
View File

@ -149,7 +149,7 @@ static void armv7m_bitband_init(void)
static void armv7m_reset(void *opaque)
{
cpu_reset((CPUState *)opaque);
cpu_state_reset((CPUARMState *)opaque);
}
/* Init CPU and memory for a v7-M based board.
@ -160,7 +160,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model)
{
CPUState *env;
CPUARMState *env;
DeviceState *nvic;
/* FIXME: make this local state. */
static qemu_irq pic[64];

2
hw/axis_dev88.c
View File

@ -247,7 +247,7 @@ void axisdev88_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPUCRISState *env;
DeviceState *dev;
SysBusDevice *s;
DriveInfo *nand;

6
hw/cris-boot.c
View File

@ -29,12 +29,12 @@
static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUCRISState *env = opaque;
struct cris_load_info *li;
li = env->load_info;
cpu_reset(env);
cpu_state_reset(env);
if (!li) {
/* nothing more to do. */
@ -60,7 +60,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return addr - 0x80000000LL;
}
void cris_load_image(CPUState *env, struct cris_load_info *li)
void cris_load_image(CPUCRISState *env, struct cris_load_info *li)
{
uint64_t entry, high;
int kcmdline_len;

2
hw/cris-boot.h
View File

@ -8,4 +8,4 @@ struct cris_load_info
target_phys_addr_t entry;
};
void cris_load_image(CPUState *env, struct cris_load_info *li);
void cris_load_image(CPUCRISState *env, struct cris_load_info *li);

4
hw/cris_pic_cpu.c
View File

@ -30,7 +30,7 @@
static void cris_pic_cpu_handler(void *opaque, int irq, int level)
{
CPUState *env = (CPUState *)opaque;
CPUCRISState *env = (CPUCRISState *)opaque;
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
if (level)
@ -39,7 +39,7 @@ static void cris_pic_cpu_handler(void *opaque, int irq, int level)
cpu_reset_interrupt(env, type);
}
qemu_irq *cris_pic_init_cpu(CPUState *env)
qemu_irq *cris_pic_init_cpu(CPUCRISState *env)
{
return qemu_allocate_irqs(cris_pic_cpu_handler, env, 2);
}

2
hw/dummy_m68k.c
View File

@ -21,7 +21,7 @@ static void dummy_m68k_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPUM68KState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size;

2
hw/etraxfs.h
View File

@ -25,7 +25,7 @@
#include "net.h"
#include "etraxfs_dma.h"
qemu_irq *cris_pic_init_cpu(CPUState *env);
qemu_irq *cris_pic_init_cpu(CPUCRISState *env);
/* Instantiate an ETRAXFS Ethernet MAC. */
static inline DeviceState *

4
hw/etraxfs_ser.c
View File

@ -78,7 +78,7 @@ static uint64_t
ser_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
struct etrax_serial *s = opaque;
D(CPUState *env = s->env);
D(CPUCRISState *env = s->env);
uint32_t r = 0;
addr >>= 2;
@ -116,7 +116,7 @@ ser_write(void *opaque, target_phys_addr_t addr,
struct etrax_serial *s = opaque;
uint32_t value = val64;
unsigned char ch = val64;
D(CPUState *env = s->env);
D(CPUCRISState *env = s->env);
D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
addr >>= 2;

2
hw/exynos4210.h
View File

@ -83,7 +83,7 @@ typedef struct Exynos4210Irq {
} Exynos4210Irq;
typedef struct Exynos4210State {
CPUState * env[EXYNOS4210_NCPUS];
CPUARMState * env[EXYNOS4210_NCPUS];
Exynos4210Irq irqs;
qemu_irq *irq_table;

2
hw/grlib.h
View File

@ -42,7 +42,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
DeviceState *grlib_irqmp_create(target_phys_addr_t base,
CPUState *env,
CPUSPARCState *env,
qemu_irq **cpu_irqs,
uint32_t nr_irqs,
set_pil_in_fn set_pil_in)

8
hw/highbank.c
View File

@ -37,12 +37,12 @@
/* Board init. */
static void highbank_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUARMState *env = opaque;
env->cp15.c15_config_base_address = GIC_BASE_ADDR;
}
static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
int n;
uint32_t smpboot[] = {
@ -66,7 +66,7 @@ static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
}
static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info)
static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
switch (info->nb_cpus) {
case 4:
@ -196,7 +196,7 @@ static void highbank_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env = NULL;
CPUARMState *env = NULL;
DeviceState *dev;
SysBusDevice *busdev;
qemu_irq *irqp;

2
hw/integratorcp.c
View File

@ -443,7 +443,7 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPUARMState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);

2
hw/kvm/apic.c
View File

@ -124,7 +124,7 @@ static void kvm_apic_vapic_base_update(APICCommonState *s)
static void do_inject_external_nmi(void *data)
{
APICCommonState *s = data;
CPUState *env = s->cpu_env;
CPUX86State *env = s->cpu_env;
uint32_t lvt;
int ret;

22
hw/kvmvapic.c
View File

@ -142,7 +142,7 @@ static void update_guest_rom_state(VAPICROMState *s)
write_guest_rom_state(s);
}
static int find_real_tpr_addr(VAPICROMState *s, CPUState *env)
static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
{
target_phys_addr_t paddr;
target_ulong addr;
@ -185,7 +185,7 @@ static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
modrm_reg(opcode[1]) == instr->modrm_reg);
}
static int evaluate_tpr_instruction(VAPICROMState *s, CPUState *env,
static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
target_ulong *pip, TPRAccess access)
{
const TPRInstruction *instr;
@ -267,7 +267,7 @@ instruction_ok:
return 0;
}
static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ulong ip)
static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
target_phys_addr_t paddr;
uint32_t rom_state_vaddr;
@ -330,7 +330,7 @@ static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ulong ip)
* cannot be accessed or is considered invalid. This also ensures that we are
* not patching the wrong guest.
*/
static int get_kpcr_number(CPUState *env)
static int get_kpcr_number(CPUX86State *env)
{
struct kpcr {
uint8_t fill1[0x1c];
@ -347,7 +347,7 @@ static int get_kpcr_number(CPUState *env)
return kpcr.number;
}
static int vapic_enable(VAPICROMState *s, CPUState *env)
static int vapic_enable(VAPICROMState *s, CPUX86State *env)
{
int cpu_number = get_kpcr_number(env);
target_phys_addr_t vapic_paddr;
@ -367,12 +367,12 @@ static int vapic_enable(VAPICROMState *s, CPUState *env)
return 0;
}
static void patch_byte(CPUState *env, target_ulong addr, uint8_t byte)
static void patch_byte(CPUX86State *env, target_ulong addr, uint8_t byte)
{
cpu_memory_rw_debug(env, addr, &byte, 1, 1);
}
static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip,
static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip,
uint32_t target)
{
uint32_t offset;
@ -382,7 +382,7 @@ static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip,
cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1);
}
static void patch_instruction(VAPICROMState *s, CPUState *env, target_ulong ip)
static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
target_phys_addr_t paddr;
VAPICHandlers *handlers;
@ -439,7 +439,7 @@ void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,
TPRAccess access)
{
VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
CPUState *env = cpu;
CPUX86State *env = cpu;
cpu_synchronize_state(env);
@ -475,7 +475,7 @@ static void vapic_enable_tpr_reporting(bool enable)
VAPICEnableTPRReporting info = {
.enable = enable,
};
CPUState *env;
CPUX86State *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
info.apic = env->apic_state;
@ -606,7 +606,7 @@ static int vapic_prepare(VAPICROMState *s)
static void vapic_write(void *opaque, target_phys_addr_t addr, uint64_t data,
unsigned int size)
{
CPUState *env = cpu_single_env;
CPUX86State *env = cpu_single_env;
target_phys_addr_t rom_paddr;
VAPICROMState *s = opaque;

10
hw/leon3.c
View File

@ -42,16 +42,16 @@
#define MAX_PILS 16
typedef struct ResetData {
CPUState *env;
CPUSPARCState *env;
uint32_t entry; /* save kernel entry in case of reset */
} ResetData;
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
CPUState *env = s->env;
CPUSPARCState *env = s->env;
cpu_reset(env);
cpu_state_reset(env);
env->halted = 0;
env->pc = s->entry;
@ -65,7 +65,7 @@ void leon3_irq_ack(void *irq_manager, int intno)
static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
{
CPUState *env = (CPUState *)opaque;
CPUSPARCState *env = (CPUSPARCState *)opaque;
assert(env != NULL);
@ -101,7 +101,7 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env;
CPUSPARCState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *prom = g_new(MemoryRegion, 1);

12
hw/lm32_boards.c
View File

@ -31,7 +31,7 @@
#include "exec-memory.h"
typedef struct {
CPUState *env;
CPULM32State *env;
target_phys_addr_t bootstrap_pc;
target_phys_addr_t flash_base;
target_phys_addr_t hwsetup_base;
@ -42,7 +42,7 @@ typedef struct {
static void cpu_irq_handler(void *opaque, int irq, int level)
{
CPUState *env = opaque;
CPULM32State *env = opaque;
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
@ -54,9 +54,9 @@ static void cpu_irq_handler(void *opaque, int irq, int level)
static void main_cpu_reset(void *opaque)
{
ResetInfo *reset_info = opaque;
CPUState *env = reset_info->env;
CPULM32State *env = reset_info->env;
cpu_reset(env);
cpu_state_reset(env);
/* init defaults */
env->pc = (uint32_t)reset_info->bootstrap_pc;
@ -75,7 +75,7 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPULM32State *env;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
@ -163,7 +163,7 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPULM32State *env;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);

2
hw/mc146818rtc.c
View File

@ -24,8 +24,6 @@
#include "hw.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "pc.h"
#include "isa.h"
#include "mc146818rtc.h"
#ifdef TARGET_I386

4
hw/mcf.h
View File

@ -17,7 +17,7 @@ void mcf_uart_mm_init(struct MemoryRegion *sysmem,
/* mcf_intc.c */
qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
target_phys_addr_t base,
CPUState *env);
CPUM68KState *env);
/* mcf_fec.c */
void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
@ -25,6 +25,6 @@ void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
/* mcf5206.c */
qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
uint32_t base, CPUState *env);
uint32_t base, CPUM68KState *env);
#endif

4
hw/mcf5206.c
View File

@ -145,7 +145,7 @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq)
/* System Integration Module. */
typedef struct {
CPUState *env;
CPUM68KState *env;
MemoryRegion iomem;
m5206_timer_state *timer[2];
void *uart[2];
@ -525,7 +525,7 @@ static const MemoryRegionOps m5206_mbar_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUState *env)
qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUM68KState *env)
{
m5206_mbar_state *s;
qemu_irq *pic;

2
hw/mcf5208.c
View File

@ -192,7 +192,7 @@ static void mcf5208evb_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;

4
hw/mcf_intc.c
View File

@ -16,7 +16,7 @@ typedef struct {
uint64_t ifr;
uint64_t enabled;
uint8_t icr[64];
CPUState *env;
CPUM68KState *env;
int active_vector;
} mcf_intc_state;
@ -139,7 +139,7 @@ static const MemoryRegionOps mcf_intc_ops = {
qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
target_phys_addr_t base,
CPUState *env)
CPUM68KState *env)
{
mcf_intc_state *s;

10
hw/microblaze_boot.c
View File

@ -35,7 +35,7 @@
static struct
{
void (*machine_cpu_reset)(CPUState *);
void (*machine_cpu_reset)(CPUMBState *);
uint32_t bootstrap_pc;
uint32_t cmdline;
uint32_t fdt;
@ -43,9 +43,9 @@ static struct
static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUMBState *env = opaque;
cpu_reset(env);
cpu_state_reset(env);
env->regs[5] = boot_info.cmdline;
env->regs[7] = boot_info.fdt;
env->sregs[SR_PC] = boot_info.bootstrap_pc;
@ -99,9 +99,9 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return addr - 0x30000000LL;
}
void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base,
void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(CPUState *))
void (*machine_cpu_reset)(CPUMBState *))
{
QemuOpts *machine_opts;

4
hw/microblaze_boot.h
View File

@ -3,8 +3,8 @@
#include "hw.h"
void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base,
void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(CPUState *));
void (*machine_cpu_reset)(CPUMBState *));
#endif /* __MICROBLAZE_BOOT __ */

4
hw/microblaze_pic_cpu.c
View File

@ -29,7 +29,7 @@
static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
{
CPUState *env = (CPUState *)opaque;
CPUMBState *env = (CPUMBState *)opaque;
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
if (level)
@ -38,7 +38,7 @@ static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
cpu_reset_interrupt(env, type);
}
qemu_irq *microblaze_pic_init_cpu(CPUState *env)
qemu_irq *microblaze_pic_init_cpu(CPUMBState *env)
{
return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2);
}

2
hw/microblaze_pic_cpu.h
View File

@ -3,6 +3,6 @@
#include "qemu-common.h"
qemu_irq *microblaze_pic_init_cpu(CPUState *env);
qemu_irq *microblaze_pic_init_cpu(CPUMBState *env);
#endif /* MICROBLAZE_PIC_CPU_H */

10
hw/milkymist.c
View File

@ -37,7 +37,7 @@
#define KERNEL_LOAD_ADDR 0x40000000
typedef struct {
CPUState *env;
CPULM32State *env;
target_phys_addr_t bootstrap_pc;
target_phys_addr_t flash_base;
target_phys_addr_t initrd_base;
@ -47,7 +47,7 @@ typedef struct {
static void cpu_irq_handler(void *opaque, int irq, int level)
{
CPUState *env = opaque;
CPULM32State *env = opaque;
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
@ -59,9 +59,9 @@ static void cpu_irq_handler(void *opaque, int irq, int level)
static void main_cpu_reset(void *opaque)
{
ResetInfo *reset_info = opaque;
CPUState *env = reset_info->env;
CPULM32State *env = reset_info->env;
cpu_reset(env);
cpu_state_reset(env);
/* init defaults */
env->pc = reset_info->bootstrap_pc;
@ -79,7 +79,7 @@ milkymist_init(ram_addr_t ram_size_not_used,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPULM32State *env;
int kernel_size;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();

4
hw/mips_cpudevs.h
View File

@ -7,9 +7,9 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
/* mips_int.c */
void cpu_mips_irq_init_cpu(CPUState *env);
void cpu_mips_irq_init_cpu(CPUMIPSState *env);
/* mips_timer.c */
void cpu_mips_clock_init(CPUState *);
void cpu_mips_clock_init(CPUMIPSState *);
#endif

12
hw/mips_fulong2e.c
View File

@ -102,7 +102,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
va_end(ap);
}
static int64_t load_kernel (CPUState *env)
static int64_t load_kernel (CPUMIPSState *env)
{
int64_t kernel_entry, kernel_low, kernel_high;
int index = 0;
@ -168,7 +168,7 @@ static int64_t load_kernel (CPUState *env)
return kernel_entry;
}
static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr)
static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr)
{
uint32_t *p;
@ -198,9 +198,9 @@ static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr)
static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUMIPSState *env = opaque;
cpu_reset(env);
cpu_state_reset(env);
/* TODO: 2E reset stuff */
if (loaderparams.kernel_filename) {
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
@ -248,7 +248,7 @@ static void network_init (void)
static void cpu_request_exit(void *opaque, int irq, int level)
{
CPUState *env = cpu_single_env;
CPUMIPSState *env = cpu_single_env;
if (env && level) {
cpu_exit(env);
@ -272,7 +272,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
i2c_bus *smbus;
int i;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
CPUState *env;
CPUMIPSState *env;
/* init CPUs */
if (cpu_model == NULL) {

6
hw/mips_int.c
View File

@ -26,7 +26,7 @@
static void cpu_mips_irq_request(void *opaque, int irq, int level)
{
CPUState *env = (CPUState *)opaque;
CPUMIPSState *env = (CPUMIPSState *)opaque;
if (irq < 0 || irq > 7)
return;
@ -44,7 +44,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
}
}
void cpu_mips_irq_init_cpu(CPUState *env)
void cpu_mips_irq_init_cpu(CPUMIPSState *env)
{
qemu_irq *qi;
int i;
@ -55,7 +55,7 @@ void cpu_mips_irq_init_cpu(CPUState *env)
}
}
void cpu_mips_soft_irq(CPUState *env, int irq, int level)
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
{
if (irq < 0 || irq > 2) {
return;

8
hw/mips_jazz.c
View File

@ -50,8 +50,8 @@ enum jazz_model_e
static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
cpu_reset(env);
CPUMIPSState *env = opaque;
cpu_state_reset(env);
}
static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
@ -97,7 +97,7 @@ static const MemoryRegionOps dma_dummy_ops = {
static void cpu_request_exit(void *opaque, int irq, int level)
{
CPUState *env = cpu_single_env;
CPUMIPSState *env = cpu_single_env;
if (env && level) {
cpu_exit(env);
@ -112,7 +112,7 @@ static void mips_jazz_init(MemoryRegion *address_space,
{
char *filename;
int bios_size, n;
CPUState *env;
CPUMIPSState *env;
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;

12
hw/mips_malta.c
View File

@ -500,7 +500,7 @@ static void network_init(void)
a3 - RAM size in bytes
*/
static void write_bootloader (CPUState *env, uint8_t *base,
static void write_bootloader (CPUMIPSState *env, uint8_t *base,
int64_t kernel_entry)
{
uint32_t *p;
@ -736,7 +736,7 @@ static int64_t load_kernel (void)
return kernel_entry;
}
static void malta_mips_config(CPUState *env)
static void malta_mips_config(CPUMIPSState *env)
{
env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
@ -744,8 +744,8 @@ static void malta_mips_config(CPUState *env)
static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
cpu_reset(env);
CPUMIPSState *env = opaque;
cpu_state_reset(env);
/* The bootloader does not need to be rewritten as it is located in a
read only location. The kernel location and the arguments table
@ -759,7 +759,7 @@ static void main_cpu_reset(void *opaque)
static void cpu_request_exit(void *opaque, int irq, int level)
{
CPUState *env = cpu_single_env;
CPUMIPSState *env = cpu_single_env;
if (env && level) {
cpu_exit(env);
@ -781,7 +781,7 @@ void mips_malta_init (ram_addr_t ram_size,
int64_t kernel_entry;
PCIBus *pci_bus;
ISABus *isa_bus;
CPUState *env;
CPUMIPSState *env;
qemu_irq *isa_irq;
qemu_irq *cpu_exit_irq;
int piix4_devfn;

8
hw/mips_mipssim.c
View File

@ -46,7 +46,7 @@ static struct _loaderparams {
} loaderparams;
typedef struct ResetData {
CPUState *env;
CPUMIPSState *env;
uint64_t vector;
} ResetData;
@ -105,9 +105,9 @@ static int64_t load_kernel(void)
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
CPUState *env = s->env;
CPUMIPSState *env = s->env;
cpu_reset(env);
cpu_state_reset(env);
env->active_tc.PC = s->vector & ~(target_ulong)1;
if (s->vector & 1) {
env->hflags |= MIPS_HFLAG_M16;
@ -140,7 +140,7 @@ mips_mipssim_init (ram_addr_t ram_size,
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
CPUState *env;
CPUMIPSState *env;
ResetData *reset_info;
int bios_size;

8
hw/mips_r4k.c
View File

@ -65,7 +65,7 @@ static const MemoryRegionOps mips_qemu_ops = {
};
typedef struct ResetData {
CPUState *env;
CPUMIPSState *env;
uint64_t vector;
} ResetData;
@ -143,9 +143,9 @@ static int64_t load_kernel(void)
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
CPUState *env = s->env;
CPUMIPSState *env = s->env;
cpu_reset(env);
cpu_state_reset(env);
env->active_tc.PC = s->vector;
}
@ -162,7 +162,7 @@ void mips_r4k_init (ram_addr_t ram_size,
MemoryRegion *bios;
MemoryRegion *iomem = g_new(MemoryRegion, 1);
int bios_size;
CPUState *env;
CPUMIPSState *env;
ResetData *reset_info;
int i;
qemu_irq *i8259;

20
hw/mips_timer.c
View File

@ -27,7 +27,7 @@
#define TIMER_FREQ 100 * 1000 * 1000
/* XXX: do not use a global */
uint32_t cpu_mips_get_random (CPUState *env)
uint32_t cpu_mips_get_random (CPUMIPSState *env)
{
static uint32_t lfsr = 1;
static uint32_t prev_idx = 0;
@ -42,7 +42,7 @@ uint32_t cpu_mips_get_random (CPUState *env)
}
/* MIPS R4K timer */
static void cpu_mips_timer_update(CPUState *env)
static void cpu_mips_timer_update(CPUMIPSState *env)
{
uint64_t now, next;
uint32_t wait;
@ -55,7 +55,7 @@ static void cpu_mips_timer_update(CPUState *env)
}
/* Expire the timer. */
static void cpu_mips_timer_expire(CPUState *env)
static void cpu_mips_timer_expire(CPUMIPSState *env)
{
cpu_mips_timer_update(env);
if (env->insn_flags & ISA_MIPS32R2) {
@ -64,7 +64,7 @@ static void cpu_mips_timer_expire(CPUState *env)
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
uint32_t cpu_mips_get_count (CPUState *env)
uint32_t cpu_mips_get_count (CPUMIPSState *env)
{
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return env->CP0_Count;
@ -83,7 +83,7 @@ uint32_t cpu_mips_get_count (CPUState *env)
}
}
void cpu_mips_store_count (CPUState *env, uint32_t count)
void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
{
if (env->CP0_Cause & (1 << CP0Ca_DC))
env->CP0_Count = count;
@ -97,7 +97,7 @@ void cpu_mips_store_count (CPUState *env, uint32_t count)
}
}
void cpu_mips_store_compare (CPUState *env, uint32_t value)
void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
{
env->CP0_Compare = value;
if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
@ -107,12 +107,12 @@ void cpu_mips_store_compare (CPUState *env, uint32_t value)
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
void cpu_mips_start_count(CPUState *env)
void cpu_mips_start_count(CPUMIPSState *env)
{
cpu_mips_store_count(env, env->CP0_Count);
}
void cpu_mips_stop_count(CPUState *env)
void cpu_mips_stop_count(CPUMIPSState *env)
{
/* Store the current value */
env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
@ -121,7 +121,7 @@ void cpu_mips_stop_count(CPUState *env)
static void mips_timer_cb (void *opaque)
{
CPUState *env;
CPUMIPSState *env;
env = opaque;
#if 0
@ -139,7 +139,7 @@ static void mips_timer_cb (void *opaque)
env->CP0_Count--;
}
void cpu_mips_clock_init (CPUState *env)
void cpu_mips_clock_init (CPUMIPSState *env)
{
env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
env->CP0_Compare = 0;

2
hw/mpc8544_guts.c
View File

@ -62,7 +62,7 @@ static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
uint32_t value = 0;
CPUState *env = cpu_single_env;
CPUPPCState *env = cpu_single_env;
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
switch (addr) {

2
hw/musicpal.c
View File

@ -1513,7 +1513,7 @@ static void musicpal_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPUARMState *env;
qemu_irq *cpu_pic;
qemu_irq pic[32];
DeviceState *dev;

2
hw/omap.h
View File

@ -813,7 +813,7 @@ struct omap_mpu_state_s {
omap3630,
} mpu_model;
CPUState *env;
CPUARMState *env;
qemu_irq *drq;

2
hw/omap1.c
View File

@ -3702,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque)
omap_lpg_reset(mpu->led[0]);
omap_lpg_reset(mpu->led[1]);
omap_clkm_reset(mpu);
cpu_reset(mpu->env);
cpu_state_reset(mpu->env);
}
static const struct omap_map_s {

2
hw/omap2.c
View File

@ -2224,7 +2224,7 @@ static void omap2_mpu_reset(void *opaque)
omap_mcspi_reset(mpu->mcspi[1]);
omap_i2c_reset(mpu->i2c[0]);
omap_i2c_reset(mpu->i2c[1]);
cpu_reset(mpu->env);
cpu_state_reset(mpu->env);
}
static int omap2_validate_addr(struct omap_mpu_state_s *s,

22
hw/pc.c
View File

@ -140,7 +140,7 @@ void cpu_smm_register(cpu_set_smm_t callback, void *arg)
smm_arg = arg;
}
void cpu_smm_update(CPUState *env)
void cpu_smm_update(CPUX86State *env)
{
if (smm_set && smm_arg && env == first_cpu)
smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
@ -148,7 +148,7 @@ void cpu_smm_update(CPUState *env)
/* IRQ handling */
int cpu_get_pic_interrupt(CPUState *env)
int cpu_get_pic_interrupt(CPUX86State *env)
{
int intno;
@ -167,7 +167,7 @@ int cpu_get_pic_interrupt(CPUState *env)
static void pic_irq_request(void *opaque, int irq, int level)
{
CPUState *env = first_cpu;
CPUX86State *env = first_cpu;
DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
if (env->apic_state) {
@ -522,7 +522,7 @@ type_init(port92_register_types)
static void handle_a20_line_change(void *opaque, int irq, int level)
{
CPUState *cpu = opaque;
CPUX86State *cpu = opaque;
/* XXX: send to all CPUs ? */
/* XXX: add logic to handle multiple A20 line sources */
@ -869,7 +869,7 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
nb_ne2k++;
}
int cpu_is_bsp(CPUState *env)
int cpu_is_bsp(CPUX86State *env)
{
/* We hard-wire the BSP to the first CPU. */
return env->cpu_index == 0;
@ -917,7 +917,7 @@ static DeviceState *apic_init(void *env, uint8_t apic_id)
void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
{
CPUState *s = opaque;
CPUX86State *s = opaque;
if (level) {
cpu_interrupt(s, CPU_INTERRUPT_SMI);
@ -926,15 +926,15 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
static void pc_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUX86State *env = opaque;
cpu_reset(env);
cpu_state_reset(env);
env->halted = !cpu_is_bsp(env);
}
static CPUState *pc_new_cpu(const char *cpu_model)
static CPUX86State *pc_new_cpu(const char *cpu_model)
{
CPUState *env;
CPUX86State *env;
env = cpu_init(cpu_model);
if (!env) {
@ -1070,7 +1070,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
static void cpu_request_exit(void *opaque, int irq, int level)
{
CPUState *env = cpu_single_env;
CPUX86State *env = cpu_single_env;
if (env && level) {
cpu_exit(env);

4
hw/petalogix_ml605_mmu.c
View File

@ -54,7 +54,7 @@
#define AXIENET_BASEADDR 0x82780000
#define AXIDMA_BASEADDR 0x84600000
static void machine_cpu_reset(CPUState *env)
static void machine_cpu_reset(CPUMBState *env)
{
env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
/* setup pvr to match kernel setting */
@ -75,7 +75,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
{
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev;
CPUState *env;
CPUMBState *env;
DriveInfo *dinfo;
int i;
target_phys_addr_t ddr_base = MEMORY_BASEADDR;

4
hw/petalogix_s3adsp1800_mmu.c
View File

@ -49,7 +49,7 @@
#define UARTLITE_BASEADDR 0x84000000
#define ETHLITE_BASEADDR 0x81000000
static void machine_cpu_reset(CPUState *env)
static void machine_cpu_reset(CPUMBState *env)
{
/* FIXME: move to machine specfic cpu reset */
env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
@ -63,7 +63,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
DeviceState *dev;
CPUState *env;
CPUMBState *env;
DriveInfo *dinfo;
int i;
target_phys_addr_t ddr_base = MEMORY_BASEADDR;

123
hw/ppc.c
View File

@ -47,10 +47,10 @@
# define LOG_TB(...) do { } while (0)
#endif
static void cpu_ppc_tb_stop (CPUState *env);
static void cpu_ppc_tb_start (CPUState *env);
static void cpu_ppc_tb_stop (CPUPPCState *env);
static void cpu_ppc_tb_start (CPUPPCState *env);
void ppc_set_irq(CPUState *env, int n_IRQ, int level)
void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level)
{
unsigned int old_pending = env->pending_interrupts;
@ -77,7 +77,7 @@ void ppc_set_irq(CPUState *env, int n_IRQ, int level)
/* PowerPC 6xx / 7xx internal IRQ controller */
static void ppc6xx_set_irq (void *opaque, int pin, int level)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
int cur_level;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@ -131,13 +131,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
/* Level sensitive - active low */
if (level) {
LOG_IRQ("%s: reset the CPU\n", __func__);
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
cpu_reset(env);
#else
qemu_system_reset_request();
#endif
cpu_interrupt(env, CPU_INTERRUPT_RESET);
}
break;
case PPC6xx_INPUT_SRESET:
@ -157,7 +151,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
}
}
void ppc6xx_irq_init (CPUState *env)
void ppc6xx_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
PPC6xx_INPUT_NB);
@ -167,7 +161,7 @@ void ppc6xx_irq_init (CPUState *env)
/* PowerPC 970 internal IRQ controller */
static void ppc970_set_irq (void *opaque, int pin, int level)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
int cur_level;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@ -214,10 +208,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
case PPC970_INPUT_HRESET:
/* Level sensitive - active low */
if (level) {
#if 0 // XXX: TOFIX
LOG_IRQ("%s: reset the CPU\n", __func__);
cpu_reset(env);
#endif
cpu_interrupt(env, CPU_INTERRUPT_RESET);
}
break;
case PPC970_INPUT_SRESET:
@ -242,7 +233,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
}
}
void ppc970_irq_init (CPUState *env)
void ppc970_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
PPC970_INPUT_NB);
@ -251,7 +242,7 @@ void ppc970_irq_init (CPUState *env)
/* POWER7 internal IRQ controller */
static void power7_set_irq (void *opaque, int pin, int level)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
env, pin, level);
@ -275,7 +266,7 @@ static void power7_set_irq (void *opaque, int pin, int level)
}
}
void ppcPOWER7_irq_init (CPUState *env)
void ppcPOWER7_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env,
POWER7_INPUT_NB);
@ -285,7 +276,7 @@ void ppcPOWER7_irq_init (CPUState *env)
/* PowerPC 40x internal IRQ controller */
static void ppc40x_set_irq (void *opaque, int pin, int level)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
int cur_level;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@ -355,7 +346,7 @@ static void ppc40x_set_irq (void *opaque, int pin, int level)
}
}
void ppc40x_irq_init (CPUState *env)
void ppc40x_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
env, PPC40x_INPUT_NB);
@ -364,7 +355,7 @@ void ppc40x_irq_init (CPUState *env)
/* PowerPC E500 internal IRQ controller */
static void ppce500_set_irq (void *opaque, int pin, int level)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
int cur_level;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@ -416,7 +407,7 @@ static void ppce500_set_irq (void *opaque, int pin, int level)
}
}
void ppce500_irq_init (CPUState *env)
void ppce500_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
env, PPCE500_INPUT_NB);
@ -430,7 +421,7 @@ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
}
uint64_t cpu_ppc_load_tbl (CPUState *env)
uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -445,7 +436,7 @@ uint64_t cpu_ppc_load_tbl (CPUState *env)
return tb;
}
static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -456,7 +447,7 @@ static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
return tb >> 32;
}
uint32_t cpu_ppc_load_tbu (CPUState *env)
uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
{
if (kvm_enabled()) {
return env->spr[SPR_TBU];
@ -473,7 +464,7 @@ static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
__func__, value, *tb_offsetp);
}
void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -484,7 +475,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
&tb_env->tb_offset, tb | (uint64_t)value);
}
static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -495,12 +486,12 @@ static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
&tb_env->tb_offset, ((uint64_t)value << 32) | tb);
}
void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
{
_cpu_ppc_store_tbu(env, value);
}
uint64_t cpu_ppc_load_atbl (CPUState *env)
uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -511,7 +502,7 @@ uint64_t cpu_ppc_load_atbl (CPUState *env)
return tb;
}
uint32_t cpu_ppc_load_atbu (CPUState *env)
uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -522,7 +513,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env)
return tb >> 32;
}
void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -533,7 +524,7 @@ void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
&tb_env->atb_offset, tb | (uint64_t)value);
}
void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -544,7 +535,7 @@ void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
&tb_env->atb_offset, ((uint64_t)value << 32) | tb);
}
static void cpu_ppc_tb_stop (CPUState *env)
static void cpu_ppc_tb_stop (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb, atb, vmclk;
@ -566,7 +557,7 @@ static void cpu_ppc_tb_stop (CPUState *env)
}
}
static void cpu_ppc_tb_start (CPUState *env)
static void cpu_ppc_tb_start (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb, atb, vmclk;
@ -587,7 +578,7 @@ static void cpu_ppc_tb_start (CPUState *env)
}
}
static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
{
ppc_tb_t *tb_env = env->tb_env;
uint32_t decr;
@ -606,7 +597,7 @@ static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
return decr;
}
uint32_t cpu_ppc_load_decr (CPUState *env)
uint32_t cpu_ppc_load_decr (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
@ -617,14 +608,14 @@ uint32_t cpu_ppc_load_decr (CPUState *env)
return _cpu_ppc_load_decr(env, tb_env->decr_next);
}
uint32_t cpu_ppc_load_hdecr (CPUState *env)
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
}
uint64_t cpu_ppc_load_purr (CPUState *env)
uint64_t cpu_ppc_load_purr (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t diff;
@ -637,23 +628,23 @@ uint64_t cpu_ppc_load_purr (CPUState *env)
/* When decrementer expires,
* all we need to do is generate or queue a CPU exception
*/
static inline void cpu_ppc_decr_excp(CPUState *env)
static inline void cpu_ppc_decr_excp(CPUPPCState *env)
{
/* Raise it */
LOG_TB("raise decrementer exception\n");
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
}
static inline void cpu_ppc_hdecr_excp(CPUState *env)
static inline void cpu_ppc_hdecr_excp(CPUPPCState *env)
{
/* Raise it */
LOG_TB("raise decrementer exception\n");
ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
}
static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
static void __cpu_ppc_store_decr (CPUPPCState *env, uint64_t *nextp,
struct QEMUTimer *timer,
void (*raise_excp)(CPUState *),
void (*raise_excp)(CPUPPCState *),
uint32_t decr, uint32_t value,
int is_excp)
{
@ -690,7 +681,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
}
}
static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,
static inline void _cpu_ppc_store_decr(CPUPPCState *env, uint32_t decr,
uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
@ -699,7 +690,7 @@ static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,
&cpu_ppc_decr_excp, decr, value, is_excp);
}
void cpu_ppc_store_decr (CPUState *env, uint32_t value)
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)
{
_cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
}
@ -709,7 +700,7 @@ static void cpu_ppc_decr_cb (void *opaque)
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,
static inline void _cpu_ppc_store_hdecr(CPUPPCState *env, uint32_t hdecr,
uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
@ -720,7 +711,7 @@ static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,
}
}
void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)
{
_cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
}
@ -730,7 +721,7 @@ static void cpu_ppc_hdecr_cb (void *opaque)
_cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
void cpu_ppc_store_purr (CPUState *env, uint64_t value)
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value)
{
ppc_tb_t *tb_env = env->tb_env;
@ -740,7 +731,7 @@ void cpu_ppc_store_purr (CPUState *env, uint64_t value)
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
ppc_tb_t *tb_env = env->tb_env;
tb_env->tb_freq = freq;
@ -755,7 +746,7 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
}
/* Set up (once) timebase frequency (in Hz) */
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
{
ppc_tb_t *tb_env;
@ -778,28 +769,28 @@ clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
/* Specific helpers for POWER & PowerPC 601 RTC */
#if 0
static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env)
{
return cpu_ppc_tb_init(env, 7812500);
}
#endif
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
{
_cpu_ppc_store_tbu(env, value);
}
uint32_t cpu_ppc601_load_rtcu (CPUState *env)
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
{
return _cpu_ppc_load_tbu(env);
}
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
{
cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
}
uint32_t cpu_ppc601_load_rtcl (CPUState *env)
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
{
return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
}
@ -823,7 +814,7 @@ struct ppc40x_timer_t {
/* Fixed interval timer */
static void cpu_4xx_fit_cb (void *opaque)
{
CPUState *env;
CPUPPCState *env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
@ -862,7 +853,7 @@ static void cpu_4xx_fit_cb (void *opaque)
}
/* Programmable interval timer */
static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
{
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
@ -891,7 +882,7 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
static void cpu_4xx_pit_cb (void *opaque)
{
CPUState *env;
CPUPPCState *env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
@ -913,7 +904,7 @@ static void cpu_4xx_pit_cb (void *opaque)
/* Watchdog timer */
static void cpu_4xx_wdt_cb (void *opaque)
{
CPUState *env;
CPUPPCState *env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
@ -978,7 +969,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
}
}
void store_40x_pit (CPUState *env, target_ulong val)
void store_40x_pit (CPUPPCState *env, target_ulong val)
{
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
@ -990,14 +981,14 @@ void store_40x_pit (CPUState *env, target_ulong val)
start_stop_pit(env, tb_env, 0);
}
target_ulong load_40x_pit (CPUState *env)
target_ulong load_40x_pit (CPUPPCState *env)
{
return cpu_ppc_load_decr(env);
}
static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
ppc_tb_t *tb_env = env->tb_env;
LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
@ -1007,7 +998,7 @@ static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
/* XXX: we should also update all timers */
}
clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq,
clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
unsigned int decr_excp)
{
ppc_tb_t *tb_env;
@ -1093,7 +1084,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
return -1;
}
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
dcr_read_cb dcr_read, dcr_write_cb dcr_write)
{
ppc_dcr_t *dcr_env;
@ -1116,7 +1107,7 @@ int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
return 0;
}
int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
int (*write_error)(int dcrn))
{
ppc_dcr_t *dcr_env;

28
hw/ppc.h
View File

@ -1,4 +1,4 @@
void ppc_set_irq (CPUState *env, int n_IRQ, int level);
void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level);
/* PowerPC hardware exceptions management helpers */
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
@ -43,32 +43,32 @@ struct ppc_tb_t {
*/
uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
/* Embedded PowerPC DCR management */
typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
int (*dcr_write_error)(int dcrn));
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
dcr_read_cb drc_read, dcr_write_cb dcr_write);
clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq,
clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
unsigned int decr_excp);
/* Embedded PowerPC reset */
void ppc40x_core_reset (CPUState *env);
void ppc40x_chip_reset (CPUState *env);
void ppc40x_system_reset (CPUState *env);
void ppc40x_core_reset (CPUPPCState *env);
void ppc40x_chip_reset (CPUPPCState *env);
void ppc40x_system_reset (CPUPPCState *env);
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
extern CPUWriteMemoryFunc * const PPC_io_write[];
extern CPUReadMemoryFunc * const PPC_io_read[];
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
void ppc40x_irq_init (CPUState *env);
void ppce500_irq_init (CPUState *env);
void ppc6xx_irq_init (CPUState *env);
void ppc970_irq_init (CPUState *env);
void ppcPOWER7_irq_init (CPUState *env);
void ppc40x_irq_init (CPUPPCState *env);
void ppce500_irq_init (CPUPPCState *env);
void ppc6xx_irq_init (CPUPPCState *env);
void ppc970_irq_init (CPUPPCState *env);
void ppcPOWER7_irq_init (CPUPPCState *env);
/* PPC machines for OpenBIOS */
enum {
@ -89,4 +89,4 @@ enum {
#define PPC_SERIAL_MM_BAUDBASE 399193
/* ppc_booke.c */
void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags);
void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags);

8
hw/ppc405.h
View File

@ -56,23 +56,23 @@ struct ppc4xx_bd_info_t {
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init);
CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init);
/* IBM STBxxx microcontrollers */
CPUState *ppc_stb025_init (MemoryRegion ram_memories[2],
CPUPPCState *ppc_stb025_init (MemoryRegion ram_memories[2],
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,

50
hw/ppc405_uc.c
View File

@ -41,7 +41,7 @@
#define DEBUG_CLOCKS
//#define DEBUG_CLOCKS_LL
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
{
ram_addr_t bdloc;
@ -169,7 +169,7 @@ static void ppc4xx_plb_reset (void *opaque)
plb->besr = 0x00000000;
}
static void ppc4xx_plb_init(CPUState *env)
static void ppc4xx_plb_init(CPUPPCState *env)
{
ppc4xx_plb_t *plb;
@ -245,7 +245,7 @@ static void ppc4xx_pob_reset (void *opaque)
pob->besr[1] = 0x0000000;
}
static void ppc4xx_pob_init(CPUState *env)
static void ppc4xx_pob_init(CPUPPCState *env)
{
ppc4xx_pob_t *pob;
@ -574,7 +574,7 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
static void ppc405_ebc_init(CPUState *env)
static void ppc405_ebc_init(CPUPPCState *env)
{
ppc4xx_ebc_t *ebc;
@ -657,7 +657,7 @@ static void ppc405_dma_reset (void *opaque)
dma->pol = 0x00000000;
}
static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
{
ppc405_dma_t *dma;
@ -960,7 +960,7 @@ static void ocm_reset (void *opaque)
ocm->dsacntl = dsacntl;
}
static void ppc405_ocm_init(CPUState *env)
static void ppc405_ocm_init(CPUPPCState *env)
{
ppc405_ocm_t *ocm;
@ -1713,7 +1713,7 @@ static void ppc40x_mal_reset (void *opaque)
mal->txeobisr = 0x00000000;
}
static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
{
ppc40x_mal_t *mal;
int i;
@ -1764,36 +1764,24 @@ static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
/*****************************************************************************/
/* SPR */
void ppc40x_core_reset (CPUState *env)
void ppc40x_core_reset (CPUPPCState *env)
{
target_ulong dbsr;
printf("Reset PowerPC core\n");
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
cpu_reset(env);
#else
qemu_system_reset_request();
#endif
cpu_interrupt(env, CPU_INTERRUPT_RESET);
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
dbsr |= 0x00000100;
env->spr[SPR_40x_DBSR] = dbsr;
}
void ppc40x_chip_reset (CPUState *env)
void ppc40x_chip_reset (CPUPPCState *env)
{
target_ulong dbsr;
printf("Reset PowerPC chip\n");
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
cpu_reset(env);
#else
qemu_system_reset_request();
#endif
cpu_interrupt(env, CPU_INTERRUPT_RESET);
/* XXX: TODO reset all internal peripherals */
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
@ -1801,13 +1789,13 @@ void ppc40x_chip_reset (CPUState *env)
env->spr[SPR_40x_DBSR] = dbsr;
}
void ppc40x_system_reset (CPUState *env)
void ppc40x_system_reset (CPUPPCState *env)
{
printf("Reset PowerPC system\n");
qemu_system_reset_request();
}
void store_40x_dbcr0 (CPUState *env, uint32_t val)
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
{
switch ((val >> 28) & 0x3) {
case 0x0:
@ -2078,7 +2066,7 @@ static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
cpc->psr |= D << 17;
}
static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
uint32_t sysclk)
{
ppc405cr_cpc_t *cpc;
@ -2108,7 +2096,7 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
qemu_register_reset(ppc405cr_cpc_reset, cpc);
}
CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
@ -2117,7 +2105,7 @@ CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
{
clk_setup_t clk_setup[PPC405CR_CLK_NB];
qemu_irq dma_irqs[4];
CPUState *env;
CPUPPCState *env;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
@ -2420,7 +2408,7 @@ static void ppc405ep_cpc_reset (void *opaque)
}
/* XXX: sysclk should be between 25 and 100 MHz */
static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
uint32_t sysclk)
{
ppc405ep_cpc_t *cpc;
@ -2457,7 +2445,7 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
#endif
}
CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
@ -2466,7 +2454,7 @@ CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
{
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUState *env;
CPUPPCState *env;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));

8
hw/ppc440_bamboo.c
View File

@ -121,7 +121,7 @@ out:
}
/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
static void mmubooke_create_initial_mapping(CPUState *env,
static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
target_phys_addr_t pa)
{
@ -145,9 +145,9 @@ static void mmubooke_create_initial_mapping(CPUState *env,
static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
cpu_reset(env);
cpu_state_reset(env);
env->gpr[1] = (16<<20) - 8;
env->gpr[3] = FDT_ADDR;
env->nip = entry;
@ -172,7 +172,7 @@ static void bamboo_init(ram_addr_t ram_size,
qemu_irq *pic;
qemu_irq *irqs;
PCIBus *pcibus;
CPUState *env;
CPUPPCState *env;
uint64_t elf_entry;
uint64_t elf_lowaddr;
target_phys_addr_t loadaddr = 0;

8
hw/ppc4xx.h
View File

@ -28,7 +28,7 @@
#include "pci.h"
/* PowerPC 4xx core initialization */
CPUState *ppc4xx_init (const char *cpu_model,
CPUPPCState *ppc4xx_init (const char *cpu_model,
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk);
@ -38,7 +38,7 @@ enum {
PPCUIC_OUTPUT_CINT = 1,
PPCUIC_OUTPUT_NB,
};
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr);
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
@ -47,13 +47,13 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[]);
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[],
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init);
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4],
target_phys_addr_t config_space,
target_phys_addr_t int_ack,
target_phys_addr_t special_cycle,

17
hw/ppc4xx_devs.c
View File

@ -38,13 +38,20 @@
# define LOG_UIC(...) do { } while (0)
#endif
static void ppc4xx_reset(void *opaque)
{
CPUPPCState *env = opaque;
cpu_state_reset(env);
}
/*****************************************************************************/
/* Generic PowerPC 4xx processor instantiation */
CPUState *ppc4xx_init (const char *cpu_model,
CPUPPCState *ppc4xx_init (const char *cpu_model,
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk)
{
CPUState *env;
CPUPPCState *env;
/* init CPUs */
env = cpu_init(cpu_model);
@ -60,7 +67,7 @@ CPUState *ppc4xx_init (const char *cpu_model,
tb_clk->opaque = env;
ppc_dcr_init(env, NULL, NULL);
/* Register qemu callbacks */
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
qemu_register_reset(ppc4xx_reset, env);
return env;
}
@ -288,7 +295,7 @@ static void ppcuic_reset (void *opaque)
}
}
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr)
{
ppcuic_t *uic;
@ -634,7 +641,7 @@ static void sdram_reset (void *opaque)
sdram->cfg = 0x00800000;
}
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories,
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,

20
hw/ppc_booke.c
View File

@ -71,7 +71,7 @@ struct booke_timer_t {
uint32_t flags;
};
static void booke_update_irq(CPUState *env)
static void booke_update_irq(CPUPPCState *env)
{
ppc_set_irq(env, PPC_INTERRUPT_DECR,
(env->spr[SPR_BOOKE_TSR] & TSR_DIS
@ -88,7 +88,7 @@ static void booke_update_irq(CPUState *env)
/* Return the location of the bit of time base at which the FIT will raise an
interrupt */
static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env)
static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
@ -106,7 +106,7 @@ static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env)
/* Return the location of the bit of time base at which the WDT will raise an
interrupt */
static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env)
static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
@ -122,7 +122,7 @@ static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env)
return wp;
}
static void booke_update_fixed_timer(CPUState *env,
static void booke_update_fixed_timer(CPUPPCState *env,
uint8_t target_bit,
uint64_t *next,
struct QEMUTimer *timer)
@ -153,7 +153,7 @@ static void booke_update_fixed_timer(CPUState *env,
static void booke_decr_cb(void *opaque)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
booke_update_irq(env);
@ -166,7 +166,7 @@ static void booke_decr_cb(void *opaque)
static void booke_fit_cb(void *opaque)
{
CPUState *env;
CPUPPCState *env;
ppc_tb_t *tb_env;
booke_timer_t *booke_timer;
@ -185,7 +185,7 @@ static void booke_fit_cb(void *opaque)
static void booke_wdt_cb(void *opaque)
{
CPUState *env;
CPUPPCState *env;
ppc_tb_t *tb_env;
booke_timer_t *booke_timer;
@ -203,13 +203,13 @@ static void booke_wdt_cb(void *opaque)
booke_timer->wdt_timer);
}
void store_booke_tsr(CPUState *env, target_ulong val)
void store_booke_tsr(CPUPPCState *env, target_ulong val)
{
env->spr[SPR_BOOKE_TSR] &= ~val;
booke_update_irq(env);
}
void store_booke_tcr(CPUState *env, target_ulong val)
void store_booke_tcr(CPUPPCState *env, target_ulong val)
{
ppc_tb_t *tb_env = env->tb_env;
booke_timer_t *booke_timer = tb_env->opaque;
@ -231,7 +231,7 @@ void store_booke_tcr(CPUState *env, target_ulong val)
}
void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags)
void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags)
{
ppc_tb_t *tb_env;
booke_timer_t *booke_timer;

11
hw/ppc_newworld.c
View File

@ -121,6 +121,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
static void ppc_core99_reset(void *opaque)
{
CPUPPCState *env = opaque;
cpu_state_reset(env);
}
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (ram_addr_t ram_size,
const char *boot_device,
@ -129,7 +136,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env = NULL;
CPUPPCState *env = NULL;
char *filename;
qemu_irq *pic, **openpic_irqs;
MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
@ -166,7 +173,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
}
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
qemu_register_reset(ppc_core99_reset, env);
}
/* allocate RAM */

11
hw/ppc_oldworld.c
View File

@ -65,6 +65,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
static void ppc_heathrow_reset(void *opaque)
{
CPUPPCState *env = opaque;
cpu_state_reset(env);
}
static void ppc_heathrow_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
@ -73,7 +80,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
const char *cpu_model)
{
MemoryRegion *sysmem = get_system_memory();
CPUState *env = NULL;
CPUPPCState *env = NULL;
char *filename;
qemu_irq *pic, **heathrow_irqs;
int linux_boot, i;
@ -104,7 +111,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
}
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, 16600000UL);
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
qemu_register_reset(ppc_heathrow_reset, env);
}
/* allocate RAM */

13
hw/ppc_prep.c
View File

@ -463,13 +463,20 @@ static const MemoryRegionOps PPC_prep_io_ops = {
static void cpu_request_exit(void *opaque, int irq, int level)
{
CPUState *env = cpu_single_env;
CPUPPCState *env = cpu_single_env;
if (env && level) {
cpu_exit(env);
}
}
static void ppc_prep_reset(void *opaque)
{
CPUPPCState *env = opaque;
cpu_state_reset(env);
}
/* PowerPC PREP hardware initialisation */
static void ppc_prep_init (ram_addr_t ram_size,
const char *boot_device,
@ -479,7 +486,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
const char *cpu_model)
{
MemoryRegion *sysmem = get_system_memory();
CPUState *env = NULL;
CPUPPCState *env = NULL;
char *filename;
nvram_t nvram;
M48t59State *m48t59;
@ -524,7 +531,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
}
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
qemu_register_reset(ppc_prep_reset, env);
}
/* allocate RAM */

16
hw/ppce500_mpc8544ds.c
View File

@ -58,7 +58,7 @@ struct boot_info
uint32_t entry;
};
static int mpc8544_load_device_tree(CPUState *env,
static int mpc8544_load_device_tree(CPUPPCState *env,
target_phys_addr_t addr,
uint32_t ramsize,
target_phys_addr_t initrd_base,
@ -178,7 +178,7 @@ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
return ffs(size >> 10) - 1;
}
static void mmubooke_create_initial_mapping(CPUState *env,
static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
target_phys_addr_t pa)
{
@ -196,9 +196,9 @@ static void mmubooke_create_initial_mapping(CPUState *env,
static void mpc8544ds_cpu_reset_sec(void *opaque)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
cpu_reset(env);
cpu_state_reset(env);
/* Secondary CPU starts in halted state for now. Needs to change when
implementing non-kernel boot. */
@ -208,10 +208,10 @@ static void mpc8544ds_cpu_reset_sec(void *opaque)
static void mpc8544ds_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUPPCState *env = opaque;
struct boot_info *bi = env->load_info;
cpu_reset(env);
cpu_state_reset(env);
/* Set initial guest state. */
env->halted = 0;
@ -231,7 +231,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
PCIBus *pci_bus;
CPUState *env = NULL;
CPUPPCState *env = NULL;
uint64_t elf_entry;
uint64_t elf_lowaddr;
target_phys_addr_t entry=0;
@ -244,7 +244,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
qemu_irq **irqs, *mpic;
DeviceState *dev;
CPUState *firstenv = NULL;
CPUPPCState *firstenv = NULL;
/* Setup CPUs */
if (cpu_model == NULL) {

8
hw/ppce500_spin.c
View File

@ -49,7 +49,7 @@ typedef struct spin_state {
} SpinState;
typedef struct spin_kick {
CPUState *env;
CPUPPCState *env;
SpinInfo *spin;
} SpinKick;
@ -73,7 +73,7 @@ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
return (ffs(size >> 10) - 1) >> 1;
}
static void mmubooke_create_initial_mapping(CPUState *env,
static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
target_phys_addr_t pa,
target_phys_addr_t len)
@ -91,7 +91,7 @@ static void mmubooke_create_initial_mapping(CPUState *env,
static void spin_kick(void *data)
{
SpinKick *kick = data;
CPUState *env = kick->env;
CPUPPCState *env = kick->env;
SpinInfo *curspin = kick->spin;
target_phys_addr_t map_size = 64 * 1024 * 1024;
target_phys_addr_t map_start;
@ -121,7 +121,7 @@ static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
{
SpinState *s = opaque;
int env_idx = addr / sizeof(SpinInfo);
CPUState *env;
CPUPPCState *env;
SpinInfo *curspin = &s->spin[env_idx];
uint8_t *curspin_p = (uint8_t*)curspin;

6
hw/pxa.h
View File

@ -65,11 +65,11 @@
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env);
/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
CPUState *env, DeviceState *pic, int lines);
CPUARMState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
/* pxa2xx_dma.c */
@ -122,7 +122,7 @@ typedef struct PXA2xxI2SState PXA2xxI2SState;
typedef struct PXA2xxFIrState PXA2xxFIrState;
typedef struct {
CPUState *env;
CPUARMState *env;
DeviceState *pic;
qemu_irq reset;
MemoryRegion sdram;

2
hw/pxa2xx.c
View File

@ -2045,7 +2045,7 @@ static void pxa2xx_reset(void *opaque, int line, int level)
PXA2xxState *s = (PXA2xxState *) opaque;
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
cpu_reset(s->env);
cpu_state_reset(s->env);
/* TODO: reset peripherals */
}
}

4
hw/pxa2xx_gpio.c
View File

@ -20,7 +20,7 @@ struct PXA2xxGPIOInfo {
qemu_irq irq0, irq1, irqX;
int lines;
int ncpu;
CPUState *cpu_env;
CPUARMState *cpu_env;
/* XXX: GNU C vectors are more suitable */
uint32_t ilevel[PXA2XX_GPIO_BANKS];
@ -249,7 +249,7 @@ static const MemoryRegionOps pxa_gpio_ops = {
};
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
CPUState *env, DeviceState *pic, int lines)
CPUARMState *env, DeviceState *pic, int lines)
{
DeviceState *dev;

4
hw/pxa2xx_pic.c
View File

@ -34,7 +34,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
CPUState *cpu_env;
CPUARMState *cpu_env;
uint32_t int_enabled[2];
uint32_t int_pending[2];
uint32_t is_fiq[2];
@ -245,7 +245,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
return 0;
}
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env)
{
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));

8
hw/r2d.c
View File

@ -192,16 +192,16 @@ static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
}
typedef struct ResetData {
CPUState *env;
CPUSH4State *env;
uint32_t vector;
} ResetData;
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
CPUState *env = s->env;
CPUSH4State *env = s->env;
cpu_reset(env);
cpu_state_reset(env);
env->pc = s->vector;
}
@ -224,7 +224,7 @@ static void r2d_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPUSH4State *env;
ResetData *reset_info;
struct SH7750State *s;
MemoryRegion *sdram = g_new(MemoryRegion, 1);

2
hw/realview.c
View File

@ -128,7 +128,7 @@ static void realview_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
enum realview_board_type board_type)
{
CPUState *env = NULL;
CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
MemoryRegion *ram_hi = g_new(MemoryRegion, 1);

6
hw/s390-virtio-bus.c
View File

@ -85,7 +85,7 @@ VirtIOS390Bus *s390_virtio_bus_init(ram_addr_t *ram_size)
return bus;
}
static void s390_virtio_irq(CPUState *env, int config_change, uint64_t token)
static void s390_virtio_irq(CPUS390XState *env, int config_change, uint64_t token)
{
if (kvm_enabled()) {
kvm_s390_virtio_irq(env, config_change, token);
@ -116,7 +116,7 @@ static int s390_virtio_device_init(VirtIOS390Device *dev, VirtIODevice *vdev)
s390_virtio_device_sync(dev);
if (dev->qdev.hotplugged) {
CPUState *env = s390_cpu_addr2state(0);
CPUS390XState *env = s390_cpu_addr2state(0);
s390_virtio_irq(env, VIRTIO_PARAM_DEV_ADD, dev->dev_offs);
}
@ -331,7 +331,7 @@ static void virtio_s390_notify(void *opaque, uint16_t vector)
{
VirtIOS390Device *dev = (VirtIOS390Device*)opaque;
uint64_t token = s390_virtio_device_vq_token(dev, vector);
CPUState *env = s390_cpu_addr2state(0);
CPUS390XState *env = s390_cpu_addr2state(0);
s390_virtio_irq(env, 0, token);
}

16
hw/s390-virtio.c
View File

@ -61,9 +61,9 @@
#define MAX_BLK_DEVS 10
static VirtIOS390Bus *s390_bus;
static CPUState **ipi_states;
static CPUS390XState **ipi_states;
CPUState *s390_cpu_addr2state(uint16_t cpu_addr)
CPUS390XState *s390_cpu_addr2state(uint16_t cpu_addr)
{
if (cpu_addr >= smp_cpus) {
return NULL;
@ -72,7 +72,7 @@ CPUState *s390_cpu_addr2state(uint16_t cpu_addr)
return ipi_states[cpu_addr];
}
int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall)
int s390_virtio_hypercall(CPUS390XState *env, uint64_t mem, uint64_t hypercall)
{
int r = 0, i;
@ -129,7 +129,7 @@ int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall)
*/
static unsigned s390_running_cpus;
void s390_add_running_cpu(CPUState *env)
void s390_add_running_cpu(CPUS390XState *env)
{
if (env->halted) {
s390_running_cpus++;
@ -138,7 +138,7 @@ void s390_add_running_cpu(CPUState *env)
}
}
unsigned s390_del_running_cpu(CPUState *env)
unsigned s390_del_running_cpu(CPUS390XState *env)
{
if (env->halted == 0) {
assert(s390_running_cpus >= 1);
@ -157,7 +157,7 @@ static void s390_init(ram_addr_t my_ram_size,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env = NULL;
CPUS390XState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
ram_addr_t kernel_size = 0;
@ -205,10 +205,10 @@ static void s390_init(ram_addr_t my_ram_size,
cpu_model = "host";
}
ipi_states = g_malloc(sizeof(CPUState *) * smp_cpus);
ipi_states = g_malloc(sizeof(CPUS390XState *) * smp_cpus);
for (i = 0; i < smp_cpus; i++) {
CPUState *tmp_env;
CPUS390XState *tmp_env;
tmp_env = cpu_init(cpu_model);
if (!env) {

2
hw/sh.h
View File

@ -11,7 +11,7 @@
struct SH7750State;
struct MemoryRegion;
struct SH7750State *sh7750_init(CPUState * cpu, struct MemoryRegion *sysmem);
struct SH7750State *sh7750_init(CPUSH4State * cpu, struct MemoryRegion *sysmem);
typedef struct {
/* The callback will be triggered if any of the designated lines change */

2
hw/shix.c
View File

@ -43,7 +43,7 @@ static void shix_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
int ret;
CPUState *env;
CPUSH4State *env;
struct SH7750State *s;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);

17
hw/spapr.c
View File

@ -110,7 +110,7 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
static int spapr_set_associativity(void *fdt, sPAPREnvironment *spapr)
{
int ret = 0, offset;
CPUState *env;
CPUPPCState *env;
char cpu_model[32];
int smt = kvmppc_smt_threads();
@ -155,7 +155,7 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
long hash_shift)
{
void *fdt;
CPUState *env;
CPUPPCState *env;
uint64_t mem_reg_property[2];
uint32_t start_prop = cpu_to_be32(initrd_base);
uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
@ -476,7 +476,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
static void emulate_spapr_hypercall(CPUState *env)
static void emulate_spapr_hypercall(CPUPPCState *env)
{
env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
}
@ -502,6 +502,13 @@ static void spapr_reset(void *opaque)
}
static void spapr_cpu_reset(void *opaque)
{
CPUPPCState *env = opaque;
cpu_state_reset(env);
}
/* pSeries LPAR / sPAPR hardware init */
static void ppc_spapr_init(ram_addr_t ram_size,
const char *boot_device,
@ -510,7 +517,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env;
CPUPPCState *env;
int i;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
@ -560,7 +567,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
}
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, TIMEBASE_FREQ);
qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
qemu_register_reset(spapr_cpu_reset, env);
env->hreset_vector = 0x60;
env->hreset_excp_prefix = 0;

4
hw/spapr.h
View File

@ -278,12 +278,12 @@ extern sPAPREnvironment *spapr;
do { } while (0)
#endif
typedef target_ulong (*spapr_hcall_fn)(CPUState *env, sPAPREnvironment *spapr,
typedef target_ulong (*spapr_hcall_fn)(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode,
target_ulong *args);
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode,
target_ulong *args);
qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num);

42
hw/spapr_hcall.c
View File

@ -92,7 +92,7 @@ static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
return rb;
}
static target_ulong h_enter(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_enter(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong flags = args[0];
@ -181,7 +181,7 @@ enum {
REMOVE_HW = 3,
};
static target_ulong remove_hpte(CPUState *env, target_ulong ptex,
static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex,
target_ulong avpn,
target_ulong flags,
target_ulong *vp, target_ulong *rp)
@ -219,7 +219,7 @@ static target_ulong remove_hpte(CPUState *env, target_ulong ptex,
return REMOVE_SUCCESS;
}
static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_remove(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong flags = args[0];
@ -265,7 +265,7 @@ static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr,
#define H_BULK_REMOVE_MAX_BATCH 4
static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_bulk_remove(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
int i;
@ -311,7 +311,7 @@ static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_protect(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong flags = args[0];
@ -356,7 +356,7 @@ static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_set_dabr(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
/* FIXME: actually implement this */
@ -375,7 +375,7 @@ static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr,
#define VPA_SHARED_PROC_OFFSET 0x9
#define VPA_SHARED_PROC_VAL 0x2
static target_ulong register_vpa(CPUState *env, target_ulong vpa)
static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
{
uint16_t size;
uint8_t tmp;
@ -410,7 +410,7 @@ static target_ulong register_vpa(CPUState *env, target_ulong vpa)
return H_SUCCESS;
}
static target_ulong deregister_vpa(CPUState *env, target_ulong vpa)
static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
{
if (env->slb_shadow) {
return H_RESOURCE;
@ -424,7 +424,7 @@ static target_ulong deregister_vpa(CPUState *env, target_ulong vpa)
return H_SUCCESS;
}
static target_ulong register_slb_shadow(CPUState *env, target_ulong addr)
static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
{
uint32_t size;
@ -451,13 +451,13 @@ static target_ulong register_slb_shadow(CPUState *env, target_ulong addr)
return H_SUCCESS;
}
static target_ulong deregister_slb_shadow(CPUState *env, target_ulong addr)
static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
{
env->slb_shadow = 0;
return H_SUCCESS;
}
static target_ulong register_dtl(CPUState *env, target_ulong addr)
static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
{
uint32_t size;
@ -482,7 +482,7 @@ static target_ulong register_dtl(CPUState *env, target_ulong addr)
return H_SUCCESS;
}
static target_ulong deregister_dtl(CPUState *emv, target_ulong addr)
static target_ulong deregister_dtl(CPUPPCState *emv, target_ulong addr)
{
env->dispatch_trace_log = 0;
env->dtl_size = 0;
@ -490,14 +490,14 @@ static target_ulong deregister_dtl(CPUState *emv, target_ulong addr)
return H_SUCCESS;
}
static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_register_vpa(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong flags = args[0];
target_ulong procno = args[1];
target_ulong vpa = args[2];
target_ulong ret = H_PARAMETER;
CPUState *tenv;
CPUPPCState *tenv;
for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
if (tenv->cpu_index == procno) {
@ -538,7 +538,7 @@ static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr,
return ret;
}
static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_cede(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
env->msr |= (1ULL << MSR_EE);
@ -549,7 +549,7 @@ static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_rtas(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong rtas_r3 = args[0];
@ -561,7 +561,7 @@ static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr,
nret, rtas_r3 + 12 + 4*nargs);
}
static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_logical_load(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong size = args[0];
@ -584,7 +584,7 @@ static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr,
return H_PARAMETER;
}
static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_logical_store(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong size = args[0];
@ -608,14 +608,14 @@ static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr,
return H_PARAMETER;
}
static target_ulong h_logical_icbi(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_logical_icbi(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
/* Nothing to do on emulation, KVM will trap this in the kernel */
return H_SUCCESS;
}
static target_ulong h_logical_dcbf(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_logical_dcbf(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
/* Nothing to do on emulation, KVM will trap this in the kernel */
@ -644,7 +644,7 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
*slot = fn;
}
target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode,
target_ulong *args)
{
if (msr_pr) {

10
hw/spapr_llan.c
View File

@ -254,7 +254,7 @@ static int check_bd(VIOsPAPRVLANDevice *dev, vlan_bd_t bd,
return 0;
}
static target_ulong h_register_logical_lan(CPUState *env,
static target_ulong h_register_logical_lan(CPUPPCState *env,
sPAPREnvironment *spapr,
target_ulong opcode,
target_ulong *args)
@ -320,7 +320,7 @@ static target_ulong h_register_logical_lan(CPUState *env,
}
static target_ulong h_free_logical_lan(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_free_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
@ -343,7 +343,7 @@ static target_ulong h_free_logical_lan(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
static target_ulong h_add_logical_lan_buffer(CPUState *env,
static target_ulong h_add_logical_lan_buffer(CPUPPCState *env,
sPAPREnvironment *spapr,
target_ulong opcode,
target_ulong *args)
@ -392,7 +392,7 @@ static target_ulong h_add_logical_lan_buffer(CPUState *env,
return H_SUCCESS;
}
static target_ulong h_send_logical_lan(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_send_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
@ -461,7 +461,7 @@ static target_ulong h_send_logical_lan(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
static target_ulong h_multicast_ctrl(CPUState *env, sPAPREnvironment *spapr,
static target_ulong h_multicast_ctrl(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];

4
hw/spapr_rtas.c
View File

@ -118,7 +118,7 @@ static void rtas_query_cpu_stopped_state(sPAPREnvironment *spapr,
uint32_t nret, target_ulong rets)
{
target_ulong id;
CPUState *env;
CPUPPCState *env;
if (nargs != 1 || nret != 2) {
rtas_st(rets, 0, -3);
@ -151,7 +151,7 @@ static void rtas_start_cpu(sPAPREnvironment *spapr,
uint32_t nret, target_ulong rets)
{
target_ulong id, start, r3;
CPUState *env;
CPUPPCState *env;
if (nargs != 3 || nret != 1) {
rtas_st(rets, 0, -3);

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