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tcg/i386: Add shortcuts for registers used in L constraint
While 64 bit hosts use the first three registers which are also used as function input parameters, 32 bit hosts use TCG_REG_EAX and TCG_REG_EDX which are not used in parameter passing. After defining new register macros for the registers used in L constraint, the patch replaces most occurrences of tcg_target_call_iarg_regs[0], tcg_target_call_iarg_regs[1] and tcg_target_call_iarg_regs[2] by those new macros. tcg_target_call_iarg_regs remains unchanged when it is used for input arguments (only with 64 bit hosts) before tcg_out_calli. A comment related to those registers was fixed, too. Signed-off-by: Stefan Weil <sw@weilnetz.de> [aurel32: build fix on i386, small optimization for i386 in the prologue] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Stefan Weil
Aurelien Jarno
parent
1b7621ad99
commit
b18212c668
@ -88,6 +88,18 @@ static const int tcg_target_call_oarg_regs[] = {
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#endif
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};
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/* Registers used with L constraint, which are the first argument
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registers on x86_64, and two random call clobbered registers on
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i386. */
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#if TCG_TARGET_REG_BITS == 64
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# define TCG_REG_L0 tcg_target_call_iarg_regs[0]
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# define TCG_REG_L1 tcg_target_call_iarg_regs[1]
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# define TCG_REG_L2 tcg_target_call_iarg_regs[2]
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#else
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# define TCG_REG_L0 TCG_REG_EAX
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# define TCG_REG_L1 TCG_REG_EDX
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#endif
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static uint8_t *tb_ret_addr;
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static void patch_reloc(uint8_t *code_ptr, int type,
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@ -179,16 +191,16 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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/* qemu_ld/st address constraint */
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case 'L':
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ct->ct |= TCG_CT_REG;
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if (TCG_TARGET_REG_BITS == 64) {
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#if TCG_TARGET_REG_BITS == 64
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tcg_regset_set32(ct->u.regs, 0, 0xffff);
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tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
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tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
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tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
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} else {
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_L2);
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#else
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tcg_regset_set32(ct->u.regs, 0, 0xff);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
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}
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
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#endif
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break;
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case 'e':
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@ -1029,8 +1041,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
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uint8_t **label_ptr, int which)
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{
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const int addrlo = args[addrlo_idx];
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const int r0 = tcg_target_call_iarg_regs[0];
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const int r1 = tcg_target_call_iarg_regs[1];
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const int r0 = TCG_REG_L0;
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const int r1 = TCG_REG_L1;
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TCGType type = TCG_TYPE_I32;
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int rexw = 0;
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@ -1192,8 +1204,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
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label_ptr, offsetof(CPUTLBEntry, addr_read));
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/* TLB Hit. */
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tcg_out_qemu_ld_direct(s, data_reg, data_reg2,
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tcg_target_call_iarg_regs[0], 0, opc);
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tcg_out_qemu_ld_direct(s, data_reg, data_reg2, TCG_REG_L0, 0, opc);
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/* jmp label2 */
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tcg_out8(s, OPC_JMP_short);
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@ -1226,14 +1237,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
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tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx],
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mem_index);
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/* XXX/FIXME: suboptimal */
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
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tcg_target_call_iarg_regs[2]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
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tcg_target_call_iarg_regs[1]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
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tcg_target_call_iarg_regs[0]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
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TCG_AREG0);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3], TCG_REG_L2);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2], TCG_REG_L1);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1], TCG_REG_L0);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0], TCG_AREG0);
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#endif
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tcg_out_calli(s, (tcg_target_long)qemu_ld_helpers[s_bits]);
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@ -1299,11 +1306,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
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use the ADDR32 prefix. For now, do nothing. */
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if (offset != GUEST_BASE) {
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tcg_out_movi(s, TCG_TYPE_I64,
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tcg_target_call_iarg_regs[0], GUEST_BASE);
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tgen_arithr(s, ARITH_ADD + P_REXW,
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tcg_target_call_iarg_regs[0], base);
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base = tcg_target_call_iarg_regs[0];
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L0, GUEST_BASE);
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tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L0, base);
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base = TCG_REG_L0;
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offset = 0;
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}
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}
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@ -1324,8 +1329,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
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/* ??? Ideally we wouldn't need a scratch register. For user-only,
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we could perform the bswap twice to restore the original value
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instead of moving to the scratch. But as it is, the L constraint
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means that the second argument reg is definitely free here. */
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int scratch = tcg_target_call_iarg_regs[1];
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means that TCG_REG_L1 is definitely free here. */
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const int scratch = TCG_REG_L1;
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switch (sizeop) {
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case 0:
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@ -1398,8 +1403,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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label_ptr, offsetof(CPUTLBEntry, addr_write));
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/* TLB Hit. */
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tcg_out_qemu_st_direct(s, data_reg, data_reg2,
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tcg_target_call_iarg_regs[0], 0, opc);
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tcg_out_qemu_st_direct(s, data_reg, data_reg2, TCG_REG_L0, 0, opc);
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/* jmp label2 */
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tcg_out8(s, OPC_JMP_short);
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@ -1434,18 +1438,14 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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stack_adjust += 4;
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#else
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tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32),
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tcg_target_call_iarg_regs[1], data_reg);
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tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], mem_index);
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TCG_REG_L1, data_reg);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_L2, mem_index);
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stack_adjust = 0;
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/* XXX/FIXME: suboptimal */
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
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tcg_target_call_iarg_regs[2]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
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tcg_target_call_iarg_regs[1]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
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tcg_target_call_iarg_regs[0]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
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TCG_AREG0);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3], TCG_REG_L2);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2], TCG_REG_L1);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1], TCG_REG_L0);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0], TCG_AREG0);
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#endif
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tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]);
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@ -1472,11 +1472,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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use the ADDR32 prefix. For now, do nothing. */
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if (offset != GUEST_BASE) {
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tcg_out_movi(s, TCG_TYPE_I64,
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tcg_target_call_iarg_regs[0], GUEST_BASE);
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tgen_arithr(s, ARITH_ADD + P_REXW,
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tcg_target_call_iarg_regs[0], base);
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base = tcg_target_call_iarg_regs[0];
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L0, GUEST_BASE);
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tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L0, base);
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base = TCG_REG_L0;
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offset = 0;
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}
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}
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@ -2061,15 +2059,17 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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#if TCG_TARGET_REG_BITS == 32
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
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(ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
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tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[1], TCG_REG_ESP,
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(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4);
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tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
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/* jmp *tb. */
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tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
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(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
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+ stack_addend);
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#else
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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#endif
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tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
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/* jmp *tb. */
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tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
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#endif
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/* TB epilogue */
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tb_ret_addr = s->code_ptr;
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