mirror of
https://github.com/xemu-project/xemu.git
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Properly implement non-execute bit on PowerPC segments and PTEs.
Fix page protection bits for PowerPC 64 MMU. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3395 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
dbdd25065e
commit
b227a8e9aa
@ -596,6 +596,7 @@ struct mmu_ctx_t {
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target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
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target_ulong ptem; /* Virtual segment ID | API */
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int key; /* Access key */
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int nx; /* Non-execute area */
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};
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/*****************************************************************************/
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@ -96,12 +96,76 @@ static always_inline void pte64_invalidate (target_ulong *pte0)
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#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
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#endif
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static always_inline int pp_check (int key, int pp, int nx)
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{
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int access;
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/* Compute access rights */
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/* When pp is 3/7, the result is undefined. Set it to noaccess */
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access = 0;
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if (key == 0) {
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switch (pp) {
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case 0x0:
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case 0x1:
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case 0x2:
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access |= PAGE_WRITE;
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/* No break here */
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case 0x3:
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case 0x6:
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access |= PAGE_READ;
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break;
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}
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} else {
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switch (pp) {
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case 0x0:
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case 0x6:
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access = 0;
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break;
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case 0x1:
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case 0x3:
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access = PAGE_READ;
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break;
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case 0x2:
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access = PAGE_READ | PAGE_WRITE;
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break;
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}
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}
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if (nx == 0)
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access |= PAGE_EXEC;
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return access;
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}
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static always_inline int check_prot (int prot, int rw, int access_type)
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{
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int ret;
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if (access_type == ACCESS_CODE) {
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if (prot & PAGE_EXEC)
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ret = 0;
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else
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ret = -2;
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} else if (rw) {
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if (prot & PAGE_WRITE)
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ret = 0;
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else
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ret = -2;
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} else {
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if (prot & PAGE_READ)
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ret = 0;
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else
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ret = -2;
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}
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return ret;
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}
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static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
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target_ulong pte0, target_ulong pte1,
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int h, int rw)
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int h, int rw, int type)
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{
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target_ulong ptem, mmask;
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int access, ret, pteh, ptev;
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int access, ret, pteh, ptev, pp;
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access = 0;
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ret = -1;
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@ -122,11 +186,15 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
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if (is_64b) {
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ptem = pte0 & PTE64_PTEM_MASK;
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mmask = PTE64_CHECK_MASK;
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pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
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ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */
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ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
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} else
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#endif
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{
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ptem = pte0 & PTE_PTEM_MASK;
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mmask = PTE_CHECK_MASK;
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pp = pte1 & 0x00000003;
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}
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if (ptem == ctx->ptem) {
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if (ctx->raddr != (target_ulong)-1) {
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@ -138,42 +206,23 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
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}
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}
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/* Compute access rights */
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if (ctx->key == 0) {
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access = PAGE_READ;
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if ((pte1 & 0x00000003) != 0x3)
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access |= PAGE_WRITE;
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} else {
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switch (pte1 & 0x00000003) {
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case 0x0:
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access = 0;
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break;
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case 0x1:
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case 0x3:
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access = PAGE_READ;
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break;
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case 0x2:
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access = PAGE_READ | PAGE_WRITE;
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break;
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}
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}
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access = pp_check(ctx->key, pp, ctx->nx);
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/* Keep the matching PTE informations */
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ctx->raddr = pte1;
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ctx->prot = access;
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if ((rw == 0 && (access & PAGE_READ)) ||
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(rw == 1 && (access & PAGE_WRITE))) {
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ret = check_prot(ctx->prot, rw, type);
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if (ret == 0) {
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/* Access granted */
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#if defined (DEBUG_MMU)
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if (loglevel != 0)
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fprintf(logfile, "PTE access granted !\n");
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#endif
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ret = 0;
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} else {
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/* Access right violation */
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#if defined (DEBUG_MMU)
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if (loglevel != 0)
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fprintf(logfile, "PTE access rejected\n");
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#endif
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ret = -2;
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}
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}
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}
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@ -181,17 +230,17 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
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return ret;
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}
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static int pte32_check (mmu_ctx_t *ctx,
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target_ulong pte0, target_ulong pte1, int h, int rw)
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static int pte32_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1,
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int h, int rw, int type)
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{
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return _pte_check(ctx, 0, pte0, pte1, h, rw);
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return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
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}
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#if defined(TARGET_PPC64)
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static int pte64_check (mmu_ctx_t *ctx,
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target_ulong pte0, target_ulong pte1, int h, int rw)
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static int pte64_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1,
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int h, int rw, int type)
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{
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return _pte_check(ctx, 1, pte0, pte1, h, rw);
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return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
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}
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#endif
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@ -353,7 +402,7 @@ static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
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rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
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}
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#endif
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switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
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switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
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case -3:
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/* TLB inconsistency */
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return -1;
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@ -398,7 +447,7 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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{
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target_ulong *BATlt, *BATut, *BATu, *BATl;
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target_ulong base, BEPIl, BEPIu, bl;
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int i;
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int i, pp;
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int ret = -1;
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#if defined (DEBUG_BATS)
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@ -447,19 +496,23 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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ctx->raddr = (*BATl & 0xF0000000) |
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((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
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(virtual & 0x0001F000);
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if (*BATl & 0x00000001)
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ctx->prot = PAGE_READ;
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if (*BATl & 0x00000002)
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ctx->prot = PAGE_WRITE | PAGE_READ;
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/* Compute access rights */
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pp = *BATl & 0x00000003;
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ctx->prot = 0;
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if (pp != 0) {
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ctx->prot = PAGE_READ | PAGE_EXEC;
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if (pp == 0x2)
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ctx->prot |= PAGE_WRITE;
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}
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ret = check_prot(ctx->prot, rw, type);
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#if defined (DEBUG_BATS)
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if (loglevel != 0) {
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if (ret == 0 && loglevel != 0) {
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fprintf(logfile, "BAT %d match: r 0x" PADDRX
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" prot=%c%c\n",
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i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
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ctx->prot & PAGE_WRITE ? 'W' : '-');
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}
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#endif
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ret = 0;
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break;
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}
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}
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@ -483,12 +536,14 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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}
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#endif
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}
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/* No hit */
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return ret;
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}
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/* PTE table lookup */
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static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
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static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
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int rw, int type)
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{
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target_ulong base, pte0, pte1;
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int i, good = -1;
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@ -501,7 +556,7 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
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if (is_64b) {
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pte0 = ldq_phys(base + (i * 16));
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pte1 = ldq_phys(base + (i * 16) + 8);
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r = pte64_check(ctx, pte0, pte1, h, rw);
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r = pte64_check(ctx, pte0, pte1, h, rw, type);
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#if defined (DEBUG_MMU)
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if (loglevel != 0) {
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fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
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@ -516,7 +571,7 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
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{
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pte0 = ldl_phys(base + (i * 8));
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pte1 = ldl_phys(base + (i * 8) + 4);
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r = pte32_check(ctx, pte0, pte1, h, rw);
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r = pte32_check(ctx, pte0, pte1, h, rw, type);
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#if defined (DEBUG_MMU)
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if (loglevel != 0) {
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fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
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@ -577,27 +632,27 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
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return ret;
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}
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static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
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static int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type)
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{
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return _find_pte(ctx, 0, h, rw);
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return _find_pte(ctx, 0, h, rw, type);
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}
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#if defined(TARGET_PPC64)
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static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
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static int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type)
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{
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return _find_pte(ctx, 1, h, rw);
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return _find_pte(ctx, 1, h, rw, type);
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}
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#endif
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static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
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int h, int rw)
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int h, int rw, int type)
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{
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#if defined(TARGET_PPC64)
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if (env->mmu_model == POWERPC_MMU_64B)
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return find_pte64(ctx, h, rw);
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return find_pte64(ctx, h, rw, type);
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#endif
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return find_pte32(ctx, h, rw);
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return find_pte32(ctx, h, rw, type);
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}
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#if defined(TARGET_PPC64)
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@ -796,7 +851,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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#if defined(TARGET_PPC64)
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int attr;
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#endif
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int ds, nx, vsid_sh, sdr_sh;
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int ds, vsid_sh, sdr_sh;
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int ret, ret2;
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#if defined(TARGET_PPC64)
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@ -812,7 +867,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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ctx->key = ((attr & 0x40) && msr_pr == 1) ||
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((attr & 0x80) && msr_pr == 0) ? 1 : 0;
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ds = 0;
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nx = attr & 0x20 ? 1 : 0;
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ctx->nx = attr & 0x20 ? 1 : 0;
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vsid_mask = 0x00003FFFFFFFFF80ULL;
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vsid_sh = 7;
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sdr_sh = 18;
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@ -825,7 +880,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
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((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
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ds = sr & 0x80000000 ? 1 : 0;
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nx = sr & 0x10000000 ? 1 : 0;
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ctx->nx = sr & 0x10000000 ? 1 : 0;
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vsid = sr & 0x00FFFFFF;
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vsid_mask = 0x01FFFFC0;
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vsid_sh = 6;
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@ -844,13 +899,13 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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#if defined (DEBUG_MMU)
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if (loglevel != 0) {
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fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
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ctx->key, ds, nx, vsid);
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ctx->key, ds, ctx->nx, vsid);
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}
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#endif
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ret = -1;
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if (!ds) {
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/* Check if instruction fetch is allowed, if needed */
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if (type != ACCESS_CODE || nx == 0) {
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if (type != ACCESS_CODE || ctx->nx == 0) {
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/* Page address translation */
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/* Primary table address */
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sdr = env->sdr1;
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@ -909,7 +964,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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}
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#endif
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/* Primary table lookup */
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ret = find_pte(env, ctx, 0, rw);
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ret = find_pte(env, ctx, 0, rw, type);
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if (ret < 0) {
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/* Secondary table lookup */
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#if defined (DEBUG_MMU)
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@ -921,7 +976,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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(uint32_t)hash, ctx->pg_addr[1]);
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}
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#endif
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ret2 = find_pte(env, ctx, 1, rw);
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ret2 = find_pte(env, ctx, 1, rw, type);
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if (ret2 != -1)
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ret = ret2;
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}
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@ -1119,76 +1174,32 @@ int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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__func__, i, zsel, zpr, rw, tlb->attr);
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}
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#endif
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if (access_type == ACCESS_CODE) {
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/* Check execute enable bit */
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switch (zpr) {
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case 0x2:
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if (msr_pr)
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goto check_exec_perm;
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goto exec_granted;
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case 0x0:
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if (msr_pr) {
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ctx->prot = 0;
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ret = -3;
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break;
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}
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/* No break here */
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case 0x1:
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check_exec_perm:
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/* Check from TLB entry */
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if (!(tlb->prot & PAGE_EXEC)) {
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ret = -3;
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} else {
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if (tlb->prot & PAGE_WRITE) {
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ctx->prot = PAGE_READ | PAGE_WRITE;
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} else {
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ctx->prot = PAGE_READ;
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}
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ret = 0;
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}
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break;
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case 0x3:
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exec_granted:
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/* All accesses granted */
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ctx->prot = PAGE_READ | PAGE_WRITE;
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ret = 0;
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break;
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}
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} else {
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switch (zpr) {
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case 0x2:
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if (msr_pr)
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goto check_rw_perm;
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goto rw_granted;
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case 0x0:
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if (msr_pr) {
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ctx->prot = 0;
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ret = -2;
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break;
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}
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/* No break here */
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case 0x1:
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check_rw_perm:
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/* Check from TLB entry */
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/* Check write protection bit */
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if (tlb->prot & PAGE_WRITE) {
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ctx->prot = PAGE_READ | PAGE_WRITE;
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ret = 0;
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} else {
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ctx->prot = PAGE_READ;
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if (rw)
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ret = -2;
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else
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ret = 0;
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}
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break;
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case 0x3:
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rw_granted:
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/* All accesses granted */
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ctx->prot = PAGE_READ | PAGE_WRITE;
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ret = 0;
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/* Check execute enable bit */
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switch (zpr) {
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case 0x2:
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if (msr_pr)
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goto check_perms;
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/* No break here */
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case 0x3:
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/* All accesses granted */
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ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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ret = 0;
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break;
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case 0x0:
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if (msr_pr) {
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ctx->prot = 0;
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ret = -2;
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break;
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}
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/* No break here */
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case 0x1:
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check_perms:
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/* Check from TLB entry */
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/* XXX: there is a problem here or in the TLB fill code... */
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ctx->prot = tlb->prot;
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ctx->prot |= PAGE_EXEC;
|
||||
ret = check_prot(ctx->prot, rw, access_type);
|
||||
break;
|
||||
}
|
||||
if (ret >= 0) {
|
||||
ctx->raddr = raddr;
|
||||
@ -1274,7 +1285,7 @@ static int check_physical (CPUState *env, mmu_ctx_t *ctx,
|
||||
int in_plb, ret;
|
||||
|
||||
ctx->raddr = eaddr;
|
||||
ctx->prot = PAGE_READ;
|
||||
ctx->prot = PAGE_READ | PAGE_EXEC;
|
||||
ret = 0;
|
||||
switch (env->mmu_model) {
|
||||
case POWERPC_MMU_32B:
|
||||
@ -1421,9 +1432,9 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
|
||||
}
|
||||
ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
|
||||
if (ret == 0) {
|
||||
ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
|
||||
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
|
||||
mmu_idx, is_softmmu);
|
||||
ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK,
|
||||
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
|
||||
mmu_idx, is_softmmu);
|
||||
} else if (ret < 0) {
|
||||
#if defined (DEBUG_MMU)
|
||||
if (loglevel != 0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user