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sh_intc: convert interrupt controller to memory API
Signed-off-by: Benoit Canet <benoit.canet@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Benoît Canet
Avi Kivity
parent
89e2945140
commit
b279e5efc0
@ -756,7 +756,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
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"cache-and-tlb", 0x08000000);
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memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
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sh_intc_init(&s->intc, NR_SOURCES,
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sh_intc_init(sysmem, &s->intc, NR_SOURCES,
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_INTC_ARRAY(mask_registers),
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_INTC_ARRAY(prio_registers));
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85
hw/sh_intc.c
85
hw/sh_intc.c
@ -219,7 +219,8 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
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#endif
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}
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static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
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static uint64_t sh_intc_read(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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struct intc_desc *desc = opaque;
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intc_enum *enum_ids = NULL;
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@ -238,7 +239,7 @@ static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
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}
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static void sh_intc_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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uint64_t value, unsigned size)
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{
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struct intc_desc *desc = opaque;
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intc_enum *enum_ids = NULL;
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@ -282,16 +283,10 @@ static void sh_intc_write(void *opaque, target_phys_addr_t offset,
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#endif
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}
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static CPUReadMemoryFunc * const sh_intc_readfn[] = {
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sh_intc_read,
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sh_intc_read,
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sh_intc_read
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};
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static CPUWriteMemoryFunc * const sh_intc_writefn[] = {
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sh_intc_write,
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sh_intc_write,
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sh_intc_write
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static const struct MemoryRegionOps sh_intc_ops = {
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.read = sh_intc_read,
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.write = sh_intc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
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@ -302,15 +297,36 @@ struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
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return NULL;
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}
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static void sh_intc_register(struct intc_desc *desc,
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unsigned long address)
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static unsigned int sh_intc_register(MemoryRegion *sysmem,
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struct intc_desc *desc,
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const unsigned long address,
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const char *type,
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const char *action,
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const unsigned int index)
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{
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if (address) {
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cpu_register_physical_memory_offset(P4ADDR(address), 4,
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desc->iomemtype, INTC_A7(address));
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cpu_register_physical_memory_offset(A7ADDR(address), 4,
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desc->iomemtype, INTC_A7(address));
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char name[60];
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MemoryRegion *iomem, *iomem_p4, *iomem_a7;
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if (!address) {
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return 0;
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}
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iomem = &desc->iomem;
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iomem_p4 = desc->iomem_aliases + index;
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iomem_a7 = iomem_p4 + 1;
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#define SH_INTC_IOMEM_FORMAT "interrupt-controller-%s-%s-%s"
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snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "p4");
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memory_region_init_alias(iomem_p4, name, iomem, INTC_A7(address), 4);
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memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
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snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "a7");
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memory_region_init_alias(iomem_a7, name, iomem, INTC_A7(address), 4);
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memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
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#undef SH_INTC_IOMEM_FORMAT
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/* used to increment aliases index */
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return 2;
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}
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static void sh_intc_register_source(struct intc_desc *desc,
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@ -415,14 +431,15 @@ void sh_intc_register_sources(struct intc_desc *desc,
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}
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}
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int sh_intc_init(struct intc_desc *desc,
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int sh_intc_init(MemoryRegion *sysmem,
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struct intc_desc *desc,
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int nr_sources,
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struct intc_mask_reg *mask_regs,
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int nr_mask_regs,
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struct intc_prio_reg *prio_regs,
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int nr_prio_regs)
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{
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unsigned int i;
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unsigned int i, j;
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desc->pending = 0;
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desc->nr_sources = nr_sources;
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@ -430,7 +447,12 @@ int sh_intc_init(struct intc_desc *desc,
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desc->nr_mask_regs = nr_mask_regs;
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desc->prio_regs = prio_regs;
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desc->nr_prio_regs = nr_prio_regs;
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/* Allocate 4 MemoryRegions per register (2 actions * 2 aliases).
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**/
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desc->iomem_aliases = g_new0(MemoryRegion,
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(nr_mask_regs + nr_prio_regs) * 4);
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j = 0;
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i = sizeof(struct intc_source) * nr_sources;
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desc->sources = g_malloc0(i);
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@ -442,15 +464,19 @@ int sh_intc_init(struct intc_desc *desc,
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desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
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desc->iomemtype = cpu_register_io_memory(sh_intc_readfn,
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sh_intc_writefn, desc,
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DEVICE_NATIVE_ENDIAN);
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memory_region_init_io(&desc->iomem, &sh_intc_ops, desc,
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"interrupt-controller", 0x100000000ULL);
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#define INT_REG_PARAMS(reg_struct, type, action, j) \
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reg_struct->action##_reg, #type, #action, j
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if (desc->mask_regs) {
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for (i = 0; i < desc->nr_mask_regs; i++) {
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struct intc_mask_reg *mr = desc->mask_regs + i;
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sh_intc_register(desc, mr->set_reg);
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sh_intc_register(desc, mr->clr_reg);
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j += sh_intc_register(sysmem, desc,
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INT_REG_PARAMS(mr, mask, set, j));
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j += sh_intc_register(sysmem, desc,
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INT_REG_PARAMS(mr, mask, clr, j));
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}
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}
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@ -458,10 +484,13 @@ int sh_intc_init(struct intc_desc *desc,
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for (i = 0; i < desc->nr_prio_regs; i++) {
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struct intc_prio_reg *pr = desc->prio_regs + i;
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sh_intc_register(desc, pr->set_reg);
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sh_intc_register(desc, pr->clr_reg);
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j += sh_intc_register(sysmem, desc,
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INT_REG_PARAMS(pr, prio, set, j));
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j += sh_intc_register(sysmem, desc,
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INT_REG_PARAMS(pr, prio, clr, j));
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}
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}
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#undef INT_REG_PARAMS
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return 0;
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}
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@ -3,6 +3,7 @@
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#include "qemu-common.h"
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#include "irq.h"
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#include "exec-memory.h"
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typedef unsigned char intc_enum;
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@ -46,6 +47,8 @@ struct intc_source {
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};
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struct intc_desc {
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MemoryRegion iomem;
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MemoryRegion *iomem_aliases;
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qemu_irq *irqs;
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struct intc_source *sources;
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int nr_sources;
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@ -53,7 +56,6 @@ struct intc_desc {
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int nr_mask_regs;
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struct intc_prio_reg *prio_regs;
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int nr_prio_regs;
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int iomemtype;
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int pending; /* number of interrupt sources that has pending set */
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};
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@ -68,7 +70,8 @@ void sh_intc_register_sources(struct intc_desc *desc,
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struct intc_group *groups,
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int nr_groups);
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int sh_intc_init(struct intc_desc *desc,
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int sh_intc_init(MemoryRegion *sysmem,
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struct intc_desc *desc,
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int nr_sources,
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struct intc_mask_reg *mask_regs,
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int nr_mask_regs,
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@ -24,7 +24,10 @@
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#include <signal.h>
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#include "cpu.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/sh_intc.h"
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#endif
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#if defined(CONFIG_USER_ONLY)
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