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target-i386: set G=1 in SMM big real mode selectors
Because the limit field's bits 31:20 is 1, G should be 1. VMX actually enforces this, let's do it for completeness in QEMU as well. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -177,22 +177,22 @@ void do_smm_enter(X86CPU *cpu)
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cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
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0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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DESC_G_MASK | DESC_A_MASK);
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}
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void helper_rsm(CPUX86State *env)
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