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target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

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For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2022-02-04 10:26:55 +08:00 committed by Alistair Francis
parent 05e6ca5e15
commit b6ecc63c56
1 changed files with 3 additions and 0 deletions
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3
target/riscv/cpu_helper.c
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@ -937,6 +937,9 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
if (pte & (PTE_D | PTE_A | PTE_U)) {
return TRANSLATE_FAIL;
}
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */