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https://github.com/xemu-project/xemu.git
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target-i386: make xmm_regs 512-bit wide
Right now, the AVX512 registers are split in many different fields: xmm_regs for the low 128 bits of the first 16 registers, ymmh_regs for the next 128 bits of the same first 16 registers, zmmh_regs for the next 256 bits of the same first 16 registers, and finally hi16_zmm_regs for the full 512 bits of the second 16 bit registers. This makes it simple to move data in and out of the xsave region, but would be a nightmare for a hypothetical TCG implementation and leads to a proliferation of [XYZ]MM_[BWLSQD] macros. Instead, this patch marshals data manually from the xsave region to a single 32x512-bit array, simplifying the macro jungle and clarifying which bits are in which vmstate subsection. The migration format is unaffected. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
a03c3e90e1
commit
b7711471f5
@ -712,24 +712,6 @@ typedef struct SegmentCache {
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uint32_t flags;
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} SegmentCache;
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typedef union {
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uint8_t _b[16];
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uint16_t _w[8];
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uint32_t _l[4];
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uint64_t _q[2];
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float32 _s[4];
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float64 _d[2];
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} XMMReg;
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typedef union {
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uint8_t _b[32];
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uint16_t _w[16];
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uint32_t _l[8];
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uint64_t _q[4];
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float32 _s[8];
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float64 _d[4];
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} YMMReg;
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typedef union {
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uint8_t _b[64];
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uint16_t _w[32];
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@ -737,7 +719,7 @@ typedef union {
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uint64_t _q[8];
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float32 _s[16];
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float64 _d[8];
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} ZMMReg;
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} XMMReg; /* really zmm */
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typedef union {
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uint8_t _b[8];
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@ -758,46 +740,18 @@ typedef struct BNDCSReg {
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} BNDCSReg;
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#ifdef HOST_WORDS_BIGENDIAN
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#define ZMM_B(n) _b[63 - (n)]
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#define ZMM_W(n) _w[31 - (n)]
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#define ZMM_L(n) _l[15 - (n)]
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#define ZMM_S(n) _s[15 - (n)]
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#define ZMM_Q(n) _q[7 - (n)]
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#define ZMM_D(n) _d[7 - (n)]
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#define YMM_B(n) _b[31 - (n)]
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#define YMM_W(n) _w[15 - (n)]
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#define YMM_L(n) _l[7 - (n)]
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#define YMM_S(n) _s[7 - (n)]
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#define YMM_Q(n) _q[3 - (n)]
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#define YMM_D(n) _d[3 - (n)]
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#define XMM_B(n) _b[15 - (n)]
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#define XMM_W(n) _w[7 - (n)]
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#define XMM_L(n) _l[3 - (n)]
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#define XMM_S(n) _s[3 - (n)]
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#define XMM_Q(n) _q[1 - (n)]
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#define XMM_D(n) _d[1 - (n)]
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#define XMM_B(n) _b[63 - (n)]
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#define XMM_W(n) _w[31 - (n)]
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#define XMM_L(n) _l[15 - (n)]
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#define XMM_S(n) _s[15 - (n)]
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#define XMM_Q(n) _q[7 - (n)]
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#define XMM_D(n) _d[7 - (n)]
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#define MMX_B(n) _b[7 - (n)]
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#define MMX_W(n) _w[3 - (n)]
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#define MMX_L(n) _l[1 - (n)]
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#define MMX_S(n) _s[1 - (n)]
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#else
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#define ZMM_B(n) _b[n]
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#define ZMM_W(n) _w[n]
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#define ZMM_L(n) _l[n]
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#define ZMM_S(n) _s[n]
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#define ZMM_Q(n) _q[n]
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#define ZMM_D(n) _d[n]
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#define YMM_B(n) _b[n]
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#define YMM_W(n) _w[n]
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#define YMM_L(n) _l[n]
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#define YMM_S(n) _s[n]
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#define YMM_Q(n) _q[n]
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#define YMM_D(n) _d[n]
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#define XMM_B(n) _b[n]
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#define XMM_W(n) _w[n]
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#define XMM_L(n) _l[n]
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@ -896,17 +850,11 @@ typedef struct CPUX86State {
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float_status mmx_status; /* for 3DNow! float ops */
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float_status sse_status;
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uint32_t mxcsr;
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XMMReg xmm_regs[CPU_NB_REGS];
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XMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
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XMMReg xmm_t0;
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MMXReg mmx_t0;
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XMMReg ymmh_regs[CPU_NB_REGS];
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uint64_t opmask_regs[NB_OPMASK_REGS];
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YMMReg zmmh_regs[CPU_NB_REGS];
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#ifdef TARGET_X86_64
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ZMMReg hi16_zmm_regs[CPU_NB_REGS];
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#endif
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/* sysenter registers */
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uint32_t sysenter_cs;
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@ -1048,7 +1048,7 @@ static int kvm_put_xsave(X86CPU *cpu)
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CPUX86State *env = &cpu->env;
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struct kvm_xsave* xsave = env->kvm_xsave_buf;
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uint16_t cwd, swd, twd;
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uint8_t *xmm;
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uint8_t *xmm, *ymmh, *zmmh;
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int i, r;
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if (!kvm_has_xsave()) {
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@ -1071,26 +1071,30 @@ static int kvm_put_xsave(X86CPU *cpu)
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sizeof env->fpregs);
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xsave->region[XSAVE_MXCSR] = env->mxcsr;
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*(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
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memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
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sizeof env->ymmh_regs);
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memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
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sizeof env->bnd_regs);
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memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
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sizeof(env->bndcs_regs));
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memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
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sizeof env->opmask_regs);
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memcpy(&xsave->region[XSAVE_ZMM_Hi256], env->zmmh_regs,
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sizeof env->zmmh_regs);
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xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
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for (i = 0; i < CPU_NB_REGS; i++, xmm += 16) {
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ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
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zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
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for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
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stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
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stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
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stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
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stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
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stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
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stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
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stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
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stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
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}
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#ifdef TARGET_X86_64
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memcpy(&xsave->region[XSAVE_Hi16_ZMM], env->hi16_zmm_regs,
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sizeof env->hi16_zmm_regs);
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memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
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16 * sizeof env->xmm_regs[16]);
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#endif
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r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
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return r;
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@ -1407,7 +1411,7 @@ static int kvm_get_xsave(X86CPU *cpu)
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CPUX86State *env = &cpu->env;
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struct kvm_xsave* xsave = env->kvm_xsave_buf;
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int ret, i;
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const uint8_t *xmm;
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const uint8_t *xmm, *ymmh, *zmmh;
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uint16_t cwd, swd, twd;
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if (!kvm_has_xsave()) {
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@ -1435,26 +1439,30 @@ static int kvm_get_xsave(X86CPU *cpu)
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memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
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sizeof env->fpregs);
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env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
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memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
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sizeof env->ymmh_regs);
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memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
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sizeof env->bnd_regs);
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memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
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sizeof(env->bndcs_regs));
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memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
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sizeof env->opmask_regs);
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memcpy(env->zmmh_regs, &xsave->region[XSAVE_ZMM_Hi256],
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sizeof env->zmmh_regs);
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xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
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for (i = 0; i < CPU_NB_REGS; i++, xmm += 16) {
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ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
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zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
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for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
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env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
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env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
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env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
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env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
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env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
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env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
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env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
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env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
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}
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#ifdef TARGET_X86_64
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memcpy(env->hi16_zmm_regs, &xsave->region[XSAVE_Hi16_ZMM],
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sizeof env->hi16_zmm_regs);
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memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
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16 * sizeof env->xmm_regs[16]);
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#endif
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return 0;
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}
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@ -46,14 +46,14 @@ static const VMStateDescription vmstate_xmm_reg = {
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VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
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vmstate_xmm_reg, XMMReg)
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/* YMMH format is the same as XMM */
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/* YMMH format is the same as XMM, but for bits 128-255 */
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static const VMStateDescription vmstate_ymmh_reg = {
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.name = "ymmh_reg",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(XMM_Q(0), XMMReg),
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VMSTATE_UINT64(XMM_Q(1), XMMReg),
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VMSTATE_UINT64(XMM_Q(2), XMMReg),
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VMSTATE_UINT64(XMM_Q(3), XMMReg),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -67,17 +67,17 @@ static const VMStateDescription vmstate_zmmh_reg = {
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(YMM_Q(0), YMMReg),
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VMSTATE_UINT64(YMM_Q(1), YMMReg),
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VMSTATE_UINT64(YMM_Q(2), YMMReg),
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VMSTATE_UINT64(YMM_Q(3), YMMReg),
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VMSTATE_UINT64(XMM_Q(4), XMMReg),
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VMSTATE_UINT64(XMM_Q(5), XMMReg),
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VMSTATE_UINT64(XMM_Q(6), XMMReg),
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VMSTATE_UINT64(XMM_Q(7), XMMReg),
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VMSTATE_END_OF_LIST()
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}
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};
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#define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start) \
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VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
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vmstate_zmmh_reg, YMMReg)
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vmstate_zmmh_reg, XMMReg)
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#ifdef TARGET_X86_64
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static const VMStateDescription vmstate_hi16_zmm_reg = {
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@ -85,21 +85,21 @@ static const VMStateDescription vmstate_hi16_zmm_reg = {
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
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VMSTATE_UINT64(XMM_Q(0), XMMReg),
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VMSTATE_UINT64(XMM_Q(1), XMMReg),
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VMSTATE_UINT64(XMM_Q(2), XMMReg),
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VMSTATE_UINT64(XMM_Q(3), XMMReg),
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VMSTATE_UINT64(XMM_Q(4), XMMReg),
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VMSTATE_UINT64(XMM_Q(5), XMMReg),
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VMSTATE_UINT64(XMM_Q(6), XMMReg),
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VMSTATE_UINT64(XMM_Q(7), XMMReg),
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VMSTATE_END_OF_LIST()
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}
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};
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#define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start) \
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VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
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vmstate_hi16_zmm_reg, ZMMReg)
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vmstate_hi16_zmm_reg, XMMReg)
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#endif
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static const VMStateDescription vmstate_bnd_regs = {
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@ -658,17 +658,16 @@ static bool avx512_needed(void *opaque)
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}
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for (i = 0; i < CPU_NB_REGS; i++) {
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#define ENV_ZMMH(reg, field) (env->zmmh_regs[reg].YMM_Q(field))
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if (ENV_ZMMH(i, 0) || ENV_ZMMH(i, 1) ||
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ENV_ZMMH(i, 2) || ENV_ZMMH(i, 3)) {
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#define ENV_XMM(reg, field) (env->xmm_regs[reg].XMM_Q(field))
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if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
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ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
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return true;
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}
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#ifdef TARGET_X86_64
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#define ENV_Hi16_ZMM(reg, field) (env->hi16_zmm_regs[reg].ZMM_Q(field))
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if (ENV_Hi16_ZMM(i, 0) || ENV_Hi16_ZMM(i, 1) ||
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ENV_Hi16_ZMM(i, 2) || ENV_Hi16_ZMM(i, 3) ||
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ENV_Hi16_ZMM(i, 4) || ENV_Hi16_ZMM(i, 5) ||
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ENV_Hi16_ZMM(i, 6) || ENV_Hi16_ZMM(i, 7)) {
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if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
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ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
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ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
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ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
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return true;
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}
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#endif
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@ -683,9 +682,9 @@ static const VMStateDescription vmstate_avx512 = {
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
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VMSTATE_ZMMH_REGS_VARS(env.zmmh_regs, X86CPU, 0),
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VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
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#ifdef TARGET_X86_64
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VMSTATE_Hi16_ZMM_REGS_VARS(env.hi16_zmm_regs, X86CPU, 0),
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VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
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#endif
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VMSTATE_END_OF_LIST()
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}
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@ -807,7 +806,7 @@ VMStateDescription vmstate_x86_cpu = {
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/* XSAVE related fields */
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VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
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VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
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VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, 0, 12),
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VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
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VMSTATE_END_OF_LIST()
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/* The above list is not sorted /wrt version numbers, watch out! */
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},
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