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qemu-macppc updates

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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-macppc-20201019' into staging

qemu-macppc updates

# gpg: Signature made Mon 19 Oct 2020 08:13:16 BST
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-macppc-20201019:
  mac_oldworld: Change PCI address of macio to match real hardware
  mac_oldworld: Drop some variables
  mac_oldworld: Drop a variable, use get_system_memory() directly
  mac_newworld: Allow loading binary ROM image
  mac_oldworld: Allow loading binary ROM image
  m48t59: remove legacy m48t59_init() function
  ppc405_boards: use qdev properties instead of legacy m48t59_init() function
  sun4u: use qdev properties instead of legacy m48t59_init() function
  sun4m: use qdev properties instead of legacy m48t59_init() function
  m48t59-isa: remove legacy m48t59_init_isa() function
  uninorth: use qdev gpios for PCI IRQs
  grackle: use qdev gpios for PCI IRQs
  macio: don't reference serial_hd() directly within the device

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-10-19 11:46:03 +01:00
commit ba2a9a9e63
13 changed files with 118 additions and 179 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/misc/macio/macio.c
View File

@ -109,8 +109,6 @@ static void macio_common_realize(PCIDevice *d, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0);
qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK);
qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4);
qdev_prop_set_chr(DEVICE(&s->escc), "chrA", serial_hd(0));
qdev_prop_set_chr(DEVICE(&s->escc), "chrB", serial_hd(1));
qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial);
qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial);
if (!qdev_realize(DEVICE(&s->escc), BUS(&s->macio_bus), errp)) {
@ -458,8 +456,6 @@ static void macio_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_OTHERS << 8;
device_class_set_props(dc, macio_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
/* Reason: Uses serial_hds in macio_instance_init */
dc->user_creatable = false;
}
static const TypeInfo macio_bus_info = {

19
hw/pci-host/grackle.c
View File

@ -28,7 +28,6 @@
#include "hw/ppc/mac.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
#include "hw/intc/heathrow_pic.h"
#include "hw/irq.h"
#include "qapi/error.h"
#include "qemu/module.h"
@ -41,7 +40,6 @@ struct GrackleState {
PCIHostState parent_obj;
uint32_t ofw_addr;
HeathrowState *pic;
qemu_irq irqs[4];
MemoryRegion pci_mmio;
MemoryRegion pci_hole;
@ -62,15 +60,6 @@ static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(s->irqs[irq_num], level);
}
static void grackle_init_irqs(GrackleState *s)
{
int i;
for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), 0x15 + i);
}
}
static void grackle_realize(DeviceState *dev, Error **errp)
{
GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
@ -85,7 +74,6 @@ static void grackle_realize(DeviceState *dev, Error **errp)
0, 4, TYPE_PCI_BUS);
pci_create_simple(phb->bus, 0, "grackle");
grackle_init_irqs(s);
}
static void grackle_init(Object *obj)
@ -106,15 +94,12 @@ static void grackle_init(Object *obj)
memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops,
DEVICE(obj), "pci-data-idx", 0x1000);
object_property_add_link(obj, "pic", TYPE_HEATHROW,
(Object **) &s->pic,
qdev_prop_allow_set_link_before_realize,
0);
sysbus_init_mmio(sbd, &phb->conf_mem);
sysbus_init_mmio(sbd, &phb->data_mem);
sysbus_init_mmio(sbd, &s->pci_hole);
sysbus_init_mmio(sbd, &s->pci_io);
qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
}
static void grackle_pci_realize(PCIDevice *d, Error **errp)

45
hw/pci-host/uninorth.c
View File

@ -32,8 +32,6 @@
#include "hw/pci-host/uninorth.h"
#include "trace.h"
static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 3;
@ -43,7 +41,7 @@ static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
UNINHostState *s = opaque;
trace_unin_set_irq(unin_irq_line[irq_num], level);
trace_unin_set_irq(irq_num, level);
qemu_set_irq(s->irqs[irq_num], level);
}
@ -112,15 +110,6 @@ static const MemoryRegionOps unin_data_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void pci_unin_init_irqs(UNINHostState *s)
{
int i;
for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
}
}
static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev)
{
UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
@ -141,7 +130,6 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp)
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
pci_unin_init_irqs(s);
/* DEC 21154 bridge */
#if 0
@ -172,15 +160,12 @@ static void pci_unin_main_init(Object *obj)
"unin-pci-hole", &s->pci_mmio,
0x80000000ULL, 0x10000000ULL);
object_property_add_link(obj, "pic", TYPE_OPENPIC,
(Object **) &s->pic,
qdev_prop_allow_set_link_before_realize,
0);
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
sysbus_init_mmio(sbd, &s->pci_hole);
sysbus_init_mmio(sbd, &s->pci_io);
qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
}
static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
@ -196,7 +181,6 @@ static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
pci_unin_init_irqs(s);
}
static void pci_u3_agp_init(Object *obj)
@ -220,15 +204,12 @@ static void pci_u3_agp_init(Object *obj)
"unin-pci-hole", &s->pci_mmio,
0x80000000ULL, 0x70000000ULL);
object_property_add_link(obj, "pic", TYPE_OPENPIC,
(Object **) &s->pic,
qdev_prop_allow_set_link_before_realize,
0);
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
sysbus_init_mmio(sbd, &s->pci_hole);
sysbus_init_mmio(sbd, &s->pci_io);
qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
}
static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
@ -244,7 +225,6 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
pci_unin_init_irqs(s);
}
static void pci_unin_agp_init(Object *obj)
@ -259,13 +239,10 @@ static void pci_unin_agp_init(Object *obj)
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
obj, "unin-agp-conf-data", 0x1000);
object_property_add_link(obj, "pic", TYPE_OPENPIC,
(Object **) &s->pic,
qdev_prop_allow_set_link_before_realize,
0);
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
}
static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
@ -281,7 +258,6 @@ static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
pci_unin_init_irqs(s);
}
static void pci_unin_internal_init(Object *obj)
@ -296,13 +272,10 @@ static void pci_unin_internal_init(Object *obj)
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
obj, "unin-pci-conf-data", 0x1000);
object_property_add_link(obj, "pic", TYPE_OPENPIC,
(Object **) &s->pic,
qdev_prop_allow_set_link_before_realize,
0);
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
}
static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)

2
hw/ppc/mac.h
View File

@ -39,10 +39,8 @@
/* SMP is not enabled, for now */
#define MAX_CPUS 1
#define BIOS_SIZE (1 * MiB)
#define NVRAM_SIZE 0x2000
#define PROM_FILENAME "openbios-ppc"
#define PROM_ADDR 0xfff00000
#define KERNEL_LOAD_ADDR 0x01000000
#define KERNEL_GAP 0x00100000

52
hw/ppc/mac_newworld.c
View File

@ -82,6 +82,8 @@
#define NDRV_VGA_FILENAME "qemu_vga.ndrv"
#define PROM_BASE 0xfff00000
#define PROM_SIZE (1 * MiB)
static void fw_cfg_boot_set(void *opaque, const char *boot_device,
Error **errp)
@ -100,7 +102,7 @@ static void ppc_core99_reset(void *opaque)
cpu_reset(CPU(cpu));
/* 970 CPUs want to get their initial IP as part of their boot protocol */
cpu->env.nip = PROM_ADDR + 0x100;
cpu->env.nip = PROM_BASE + 0x100;
}
/* PowerPC Mac99 hardware initialisation */
@ -123,6 +125,7 @@ static void ppc_core99_init(MachineState *machine)
UNINHostState *uninorth_pci;
PCIBus *pci_bus;
PCIDevice *macio;
ESCCState *escc;
bool has_pmu, has_adb;
MACIOIDEState *macio_ide;
BusState *adb_bus;
@ -153,25 +156,29 @@ static void ppc_core99_init(MachineState *machine)
/* allocate RAM */
memory_region_add_subregion(get_system_memory(), 0, machine->ram);
/* allocate and load BIOS */
memory_region_init_rom(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
/* allocate and load firmware ROM */
memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE,
&error_fatal);
memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
if (bios_name == NULL)
if (!bios_name) {
bios_name = PROM_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
if (filename) {
/* Load OpenBIOS (ELF) */
bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
if (bios_size <= 0) {
/* or load binary ROM image */
bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
}
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
if (bios_size < 0 || bios_size > PROM_SIZE) {
error_report("could not load PowerPC bios '%s'", bios_name);
exit(1);
}
@ -302,8 +309,6 @@ static void ppc_core99_init(MachineState *machine)
/* 970 gets a U3 bus */
/* Uninorth AGP bus */
dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
&error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
@ -316,32 +321,38 @@ static void ppc_core99_init(MachineState *machine)
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
}
machine_arch = ARCH_MAC99_U3;
} else {
/* Use values found on a real PowerMac */
/* Uninorth AGP bus */
dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
&error_abort);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
}
/* Uninorth internal bus */
dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
&error_abort);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xf4800000);
sysbus_mmio_map(s, 1, 0xf4c00000);
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
}
/* Uninorth main bus */
dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
&error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
@ -354,6 +365,10 @@ static void ppc_core99_init(MachineState *machine)
sysbus_mmio_map(s, 0, 0xf2800000);
sysbus_mmio_map(s, 1, 0xf2c00000);
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
}
machine_arch = ARCH_MAC99;
}
@ -380,6 +395,11 @@ static void ppc_core99_init(MachineState *machine)
qdev_prop_set_bit(dev, "has-adb", has_adb);
object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev),
&error_abort);
escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
pci_realize_and_unref(macio, pci_bus, &error_fatal);
/* We only emulate 2 out of 3 IDE controllers for now */

80
hw/ppc/mac_oldworld.c
View File

@ -59,6 +59,8 @@
#define NDRV_VGA_FILENAME "qemu_vga.ndrv"
#define GRACKLE_BASE 0xfec00000
#define PROM_BASE 0xffc00000
#define PROM_SIZE (4 * MiB)
static void fw_cfg_boot_set(void *opaque, const char *boot_device,
Error **errp)
@ -81,24 +83,22 @@ static void ppc_heathrow_reset(void *opaque)
static void ppc_heathrow_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
const char *boot_device = machine->boot_order;
MemoryRegion *sysmem = get_system_memory();
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
int linux_boot, i;
int i;
MemoryRegion *bios = g_new(MemoryRegion, 1);
uint32_t kernel_base, initrd_base, cmdline_base = 0;
int32_t kernel_size, initrd_size;
PCIBus *pci_bus;
PCIDevice *macio;
MACIOIDEState *macio_ide;
ESCCState *escc;
SysBusDevice *s;
DeviceState *dev, *pic_dev;
BusState *adb_bus;
uint64_t bios_addr;
int bios_size;
unsigned int smp_cpus = machine->smp.cpus;
uint16_t ppc_boot_device;
@ -106,8 +106,6 @@ static void ppc_heathrow_init(MachineState *machine)
void *fw_cfg;
uint64_t tbfreq;
linux_boot = (kernel_filename != NULL);
/* init CPUs */
for (i = 0; i < smp_cpus; i++) {
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
@ -125,31 +123,39 @@ static void ppc_heathrow_init(MachineState *machine)
exit(1);
}
memory_region_add_subregion(sysmem, 0, machine->ram);
memory_region_add_subregion(get_system_memory(), 0, machine->ram);
/* allocate and load BIOS */
memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
/* allocate and load firmware ROM */
memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE,
&error_fatal);
memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
if (bios_name == NULL)
if (!bios_name) {
bios_name = PROM_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_add_subregion(sysmem, PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
if (filename) {
bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL, NULL,
1, PPC_ELF_MACHINE, 0, 0);
/* Load OpenBIOS (ELF) */
bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr,
NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
/* Unfortunately, load_elf sign-extends reading elf32 */
bios_addr = (uint32_t)bios_addr;
if (bios_size <= 0) {
/* or if could not load ELF try loading a binary ROM image */
bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
bios_addr = PROM_BASE;
}
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) {
error_report("could not load PowerPC bios '%s'", bios_name);
exit(1);
}
if (linux_boot) {
if (machine->kernel_filename) {
int bswap_needed;
#ifdef BSWAP_NEEDED
@ -158,29 +164,32 @@ static void ppc_heathrow_init(MachineState *machine)
bswap_needed = 0;
#endif
kernel_base = KERNEL_LOAD_ADDR;
kernel_size = load_elf(kernel_filename, NULL,
kernel_size = load_elf(machine->kernel_filename, NULL,
translate_kernel_address, NULL, NULL, NULL,
NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, kernel_base,
kernel_size = load_aout(machine->kernel_filename, kernel_base,
ram_size - kernel_base, bswap_needed,
TARGET_PAGE_SIZE);
if (kernel_size < 0)
kernel_size = load_image_targphys(kernel_filename,
kernel_size = load_image_targphys(machine->kernel_filename,
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
error_report("could not load kernel '%s'",
machine->kernel_filename);
exit(1);
}
/* load initrd */
if (initrd_filename) {
initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
initrd_size = load_image_targphys(initrd_filename, initrd_base,
if (machine->initrd_filename) {
initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
KERNEL_GAP);
initrd_size = load_image_targphys(machine->initrd_filename,
initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
initrd_filename);
machine->initrd_filename);
exit(1);
}
cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
@ -252,10 +261,9 @@ static void ppc_heathrow_init(MachineState *machine)
/* Grackle PCI host bridge */
dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
&error_abort);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, GRACKLE_BASE);
sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
/* PCI hole */
@ -265,6 +273,10 @@ static void ppc_heathrow_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), 0xfe000000,
sysbus_mmio_get_region(s, 3));
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x15 + i));
}
pci_bus = PCI_HOST_BRIDGE(dev)->bus;
pci_vga_init(pci_bus);
@ -276,11 +288,16 @@ static void ppc_heathrow_init(MachineState *machine)
ide_drive_get(hd, ARRAY_SIZE(hd));
/* MacIO */
macio = pci_new(-1, TYPE_OLDWORLD_MACIO);
macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO);
dev = DEVICE(macio);
qdev_prop_set_uint64(dev, "frequency", tbfreq);
object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev),
&error_abort);
escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
pci_realize_and_unref(macio, pci_bus, &error_fatal);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
@ -324,9 +341,10 @@ static void ppc_heathrow_init(MachineState *machine)
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
if (machine->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
machine->kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}

10
hw/ppc/ppc405_boards.c
View File

@ -28,6 +28,8 @@
#include "qemu-common.h"
#include "cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "ppc405.h"
#include "hw/rtc/m48t59.h"
#include "hw/block/flash.h"
@ -145,6 +147,8 @@ static void ref405ep_init(MachineState *machine)
char *filename;
ppc4xx_bd_info_t bd;
CPUPPCState *env;
DeviceState *dev;
SysBusDevice *s;
qemu_irq *pic;
MemoryRegion *bios;
MemoryRegion *sram = g_new(MemoryRegion, 1);
@ -227,7 +231,11 @@ static void ref405ep_init(MachineState *machine)
/* Register FPGA */
ref405ep_fpga_init(sysmem, 0xF0300000);
/* Register NVRAM */
m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
dev = qdev_new("sysbus-m48t08");
qdev_prop_set_int32(dev, "base-year", 1968);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xF0000000);
/* Load kernel */
linux_boot = (kernel_filename != NULL);
if (linux_boot) {

25
hw/rtc/m48t59-isa.c
View File

@ -58,31 +58,6 @@ static M48txxInfo m48txx_isa_info[] = {
}
};
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
int base_year, int model)
{
ISADevice *isa_dev;
DeviceState *dev;
int i;
for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
if (m48txx_isa_info[i].size != size ||
m48txx_isa_info[i].model != model) {
continue;
}
isa_dev = isa_new(m48txx_isa_info[i].bus_name);
dev = DEVICE(isa_dev);
qdev_prop_set_uint32(dev, "iobase", io_base);
qdev_prop_set_int32(dev, "base-year", base_year);
isa_realize_and_unref(isa_dev, bus, &error_fatal);
return NVRAM(dev);
}
assert(false);
return NULL;
}
static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
{
M48txxISAState *d = M48TXX_ISA(obj);

35
hw/rtc/m48t59.c
View File

@ -564,41 +564,6 @@ const MemoryRegionOps m48t59_io_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
/* Initialisation routine */
Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
uint32_t io_base, uint16_t size, int base_year,
int model)
{
DeviceState *dev;
SysBusDevice *s;
int i;
for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
if (m48txx_sysbus_info[i].size != size ||
m48txx_sysbus_info[i].model != model) {
continue;
}
dev = qdev_new(m48txx_sysbus_info[i].bus_name);
qdev_prop_set_int32(dev, "base-year", base_year);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, IRQ);
if (io_base != 0) {
memory_region_add_subregion(get_system_io(), io_base,
sysbus_mmio_get_region(s, 1));
}
if (mem_base != 0) {
sysbus_mmio_map(s, 0, mem_base);
}
return NVRAM(s);
}
assert(false);
return NULL;
}
void m48t59_realize_common(M48t59State *s, Error **errp)
{
s->buffer = g_malloc0(s->size);

10
hw/sparc/sun4m.c
View File

@ -837,7 +837,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
{
DeviceState *slavio_intctl;
unsigned int i;
void *nvram;
Nvram *nvram;
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
qemu_irq fdc_tc;
unsigned long kernel_size;
@ -966,7 +966,13 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
}
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
dev = qdev_new("sysbus-m48t08");
qdev_prop_set_int32(dev, "base-year", 1968);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, slavio_irq[0]);
sysbus_mmio_map(s, 0, hwdef->nvram_base);
nvram = NVRAM(dev);
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);

7
hw/sparc64/sun4u.c
View File

@ -671,10 +671,13 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
pci_ide_create_devs(pci_dev);
/* Map NVRAM into I/O (ebus) space */
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
s = SYS_BUS_DEVICE(nvram);
dev = qdev_new("sysbus-m48t59");
qdev_prop_set_int32(dev, "base-year", 1968);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
sysbus_mmio_get_region(s, 0));
nvram = NVRAM(dev);
initrd_size = 0;
initrd_addr = 0;

2
include/hw/pci-host/uninorth.h
View File

@ -26,7 +26,6 @@
#define UNINORTH_H
#include "hw/pci/pci_host.h"
#include "hw/ppc/openpic.h"
#include "qom/object.h"
/* UniNorth version */
@ -51,7 +50,6 @@ struct UNINHostState {
PCIHostState parent_obj;
uint32_t ofw_addr;
OpenPICState *pic;
qemu_irq irqs[4];
MemoryRegion pci_mmio;
MemoryRegion pci_hole;

6
include/hw/rtc/m48t59.h
View File

@ -47,10 +47,4 @@ struct NvramClass {
void (*toggle_lock)(Nvram *obj, int lock);
};
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
int base_year, int type);
Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
uint32_t io_base, uint16_t size, int base_year,
int type);
#endif /* HW_M48T59_H */