xemu-project/xemu
1
0
Fork 0
mirror of https://github.com/xemu-project/xemu.git synced 2024-11-30 23:10:38 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Hexagon (target/hexagon) register fields

Browse Source 
Declare bitfields within registers such as user status register (USR)

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1612763186-18161-12-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Taylor Simpson 2021-02-07 23:46:01 -06:00 committed by Richard Henderson
parent 3e474055c7
commit ba385122b5
3 changed files with 104 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
target/hexagon/reg_fields.c Normal file
View File

@ -0,0 +1,27 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "reg_fields.h"
const RegField reg_field_info[] = {
#define DEF_REG_FIELD(TAG, START, WIDTH) \
{ START, WIDTH },
#include "reg_fields_def.h.inc"
{ 0, 0 }
#undef DEF_REG_FIELD
};

36
target/hexagon/reg_fields.h Normal file
View File

@ -0,0 +1,36 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HEXAGON_REG_FIELDS_H
#define HEXAGON_REG_FIELDS_H
typedef struct {
int offset;
int width;
} RegField;
extern const RegField reg_field_info[];
enum {
#define DEF_REG_FIELD(TAG, START, WIDTH) \
TAG,
#include "reg_fields_def.h.inc"
NUM_REG_FIELDS
#undef DEF_REG_FIELD
};
#endif

41
target/hexagon/reg_fields_def.h.inc Normal file
View File

@ -0,0 +1,41 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
/*
* For registers that have individual fields, explain them here
* DEF_REG_FIELD(tag,
* bit start offset,
* width
*/
/* USR fields */
DEF_REG_FIELD(USR_OVF, 0, 1)
DEF_REG_FIELD(USR_FPINVF, 1, 1)
DEF_REG_FIELD(USR_FPDBZF, 2, 1)
DEF_REG_FIELD(USR_FPOVFF, 3, 1)
DEF_REG_FIELD(USR_FPUNFF, 4, 1)
DEF_REG_FIELD(USR_FPINPF, 5, 1)
DEF_REG_FIELD(USR_LPCFG, 8, 2)
DEF_REG_FIELD(USR_FPRND, 22, 2)
DEF_REG_FIELD(USR_FPINVE, 25, 1)
DEF_REG_FIELD(USR_FPDBZE, 26, 1)
DEF_REG_FIELD(USR_FPOVFE, 27, 1)
DEF_REG_FIELD(USR_FPUNFE, 28, 1)
DEF_REG_FIELD(USR_FPINPE, 29, 1)