Renesas patches (SH4 and RX)

- Fix few warnings (Thomas Huth) - Fix typos (Lichang Zhao, Chetan Pant) CI jobs results: . https://cirrus-ci.com/build/6368903343374336 . https://gitlab.com/philmd/qemu/-/pipelines/207919103 . https://travis-ci.org/github/philmd/qemu/builds/739133105 -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAl+XW2sACgkQ4+MsLN6t wN5Z+RAAtkD1zbjh3w0zC4kM6npJYpyvIruhQRqpHnHrgTqN6nzmxYquMprRHliI kgiSO6W2nNCqFWnFXBuve82NeWQhhyMZGA4iggCy45a6W/j5t8bfPRdWeFHQjd0O kfakFlB+IFU5lQ2BroRe44IcmGkCMMtuRYK/HCvHZz1a058AOfBpr0egi6cZOXas DEMJNw+FFhcWb6DUaDl0iPKKawzH7GhMkrpVLzWbUd4rrIwzYjDU5w7yp5f1GXG0 63vCO/3vUAmi8cKzTluKBN4pQhzC+lWNCm9MGUVbunHfPWZImfkdnrwJPE95hwuT Dx9WVEsX6P6y3/pN5q7a9J0IdP6BUqIem+yhT4QOWvfoBl/MqqtgwfJh/AcYrrdz LHmQpHyw1aDxWGP4CODdeuTaIA216I6YJosFYb/JHoh2Gw3CUunMsQPZCXz+srQG p+1MZMHPF4A1cElSvX9dtxWxXrHcqZoKOKK6bu9Q6tHSXJ26DMkY35neS7+hBe9B QRdT58DgnR0dBjaF+SGXe/EWqIq0xBNsvwuxZ+gD0sefh+nDyAVnBpYdOERNFY0O 10FWY9yuEYjDAQK0mmjkMbp9xfgQ3YtRCoVAt/YOWBl4nWDlNagX4iSwBvR0i8Xg DtOX7haw3XCQvP2j1pbhbjYXosab/sjxcWo7SrPdNGd7cU74jzY= =dMmS -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging Renesas patches (SH4 and RX) - Fix few warnings (Thomas Huth) - Fix typos (Lichang Zhao, Chetan Pant) CI jobs results: . https://cirrus-ci.com/build/6368903343374336 . https://gitlab.com/philmd/qemu/-/pipelines/207919103 . https://travis-ci.org/github/philmd/qemu/builds/739133105 # gpg: Signature made Mon 26 Oct 2020 23:27:39 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/renesas-20201027: target/rx: Fix Lesser GPL version number target/rx: Fix some comment spelling errors target/sh4: fix some comment spelling errors target/sh4: Update coding style to make checkpatch.pl happy hw/timer/sh_timer: Remove superfluous "break" statements hw/timer/sh_timer: Silence warnings about missing fallthrough statements hw/timer/sh_timer: Coding style clean-up elf: Add EM_RX definition Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-23 19:49:43 +00:00 · 2020-10-28 16:25:31 +00:00 · 2020-10-28 16:25:31 +00:00 · bbc48d2bcb
commit bbc48d2bcb
parent 5c27a85518 81c7643340
8 changed files with 74 additions and 42 deletions
--- a/hw/timer/sh_timer.c
+++ b/hw/timer/sh_timer.c
@ -117,35 +117,55 @@ static void sh_timer_write(void *opaque, hwaddr offset,
        case 2: freq >>= 6; break;
        case 3: freq >>= 8; break;
        case 4: freq >>= 10; break;
-	case 6:
-	case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
-	default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
+        case 6:
+        case 7:
+            if (s->feat & TIMER_FEAT_EXTCLK) {
+                break;
+            }
+            /* fallthrough */
+        default:
+            hw_error("sh_timer_write: Reserved TPSC value\n");
        }
        switch ((value & TIMER_TCR_CKEG) >> 3) {
-	case 0: break;
+        case 0:
+            break;
        case 1:
        case 2:
-        case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
-	default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
+        case 3:
+            if (s->feat & TIMER_FEAT_EXTCLK) {
+                break;
+            }
+            /* fallthrough */
+        default:
+            hw_error("sh_timer_write: Reserved CKEG value\n");
        }
        switch ((value & TIMER_TCR_ICPE) >> 6) {
-	case 0: break;
+        case 0:
+            break;
        case 2:
-        case 3: if (s->feat & TIMER_FEAT_CAPT) break;
-	default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
+        case 3:
+            if (s->feat & TIMER_FEAT_CAPT) {
+                break;
+            }
+            /* fallthrough */
+        default:
+            hw_error("sh_timer_write: Reserved ICPE value\n");
        }
-	if ((value & TIMER_TCR_UNF) == 0)
+        if ((value & TIMER_TCR_UNF) == 0) {
            s->int_level = 0;
+        }

-	value &= ~TIMER_TCR_UNF;
+        value &= ~TIMER_TCR_UNF;

-	if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
+        if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) {
            hw_error("sh_timer_write: Reserved ICPF value\n");
+        }

-	value &= ~TIMER_TCR_ICPF; /* capture not supported */
+        value &= ~TIMER_TCR_ICPF; /* capture not supported */

-	if (value & TIMER_TCR_RESERVED)
+        if (value & TIMER_TCR_RESERVED) {
            hw_error("sh_timer_write: Reserved TCR bits set\n");
+        }
        s->tcr = value;
        ptimer_set_limit(s->timer, s->tcor, 0);
        ptimer_set_freq(s->timer, freq);
@ -158,8 +178,9 @@ static void sh_timer_write(void *opaque, hwaddr offset,
    case OFFSET_TCPR:
        if (s->feat & TIMER_FEAT_CAPT) {
            s->tcpr = value;
-	    break;
-	}
+            break;
+        }
+        /* fallthrough */
    default:
        hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
    }
@ -241,8 +262,9 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset,
 #endif

    if (offset >= 0x20) {
-        if (!(s->feat & TMU012_FEAT_3CHAN))
-	    hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
+        if (!(s->feat & TMU012_FEAT_3CHAN)) {
+            hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
+        }
        return sh_timer_read(s->timer[2], offset - 0x20);
    }

@ -272,33 +294,36 @@ static void tmu012_write(void *opaque, hwaddr offset,
 #endif

    if (offset >= 0x20) {
-        if (!(s->feat & TMU012_FEAT_3CHAN))
-	    hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
+        if (!(s->feat & TMU012_FEAT_3CHAN)) {
+            hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
+        }
        sh_timer_write(s->timer[2], offset - 0x20, value);
-	return;
+        return;
    }

    if (offset >= 0x14) {
        sh_timer_write(s->timer[1], offset - 0x14, value);
-	return;
+        return;
    }

    if (offset >= 0x08) {
        sh_timer_write(s->timer[0], offset - 0x08, value);
-	return;
+        return;
    }

    if (offset == 4) {
        sh_timer_start_stop(s->timer[0], value & (1 << 0));
        sh_timer_start_stop(s->timer[1], value & (1 << 1));
-        if (s->feat & TMU012_FEAT_3CHAN)
+        if (s->feat & TMU012_FEAT_3CHAN) {
            sh_timer_start_stop(s->timer[2], value & (1 << 2));
-	else
-            if (value & (1 << 2))
+        } else {
+            if (value & (1 << 2)) {
                hw_error("tmu012_write: Bad channel\n");
+            }
+        }

-	s->tstr = value;
-	return;
+        s->tstr = value;
+        return;
    }

    if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
@ -314,8 +339,8 @@ static const MemoryRegionOps tmu012_ops = {

 void tmu012_init(MemoryRegion *sysmem, hwaddr base,
                 int feat, uint32_t freq,
-		 qemu_irq ch0_irq, qemu_irq ch1_irq,
-		 qemu_irq ch2_irq0, qemu_irq ch2_irq1)
+                 qemu_irq ch0_irq, qemu_irq ch1_irq,
+                 qemu_irq ch2_irq0, qemu_irq ch2_irq1)
 {
    tmu012_state *s;
    int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
@ -324,9 +349,10 @@ void tmu012_init(MemoryRegion *sysmem, hwaddr base,
    s->feat = feat;
    s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
    s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
-    if (feat & TMU012_FEAT_3CHAN)
+    if (feat & TMU012_FEAT_3CHAN) {
        s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
-				    ch2_irq0); /* ch2_irq1 not supported */
+                                    ch2_irq0); /* ch2_irq1 not supported */
+    }

    memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
                          "timer", 0x100000000ULL);
--- a/include/elf.h
+++ b/include/elf.h
@ -172,6 +172,8 @@ typedef struct mips_elf_abiflags_v0 {

 #define EM_UNICORE32    110     /* UniCore32 */

+#define EM_RX           173     /* Renesas RX family */
+
 #define EM_RISCV        243     /* RISC-V */

 #define EM_NANOMIPS     249     /* Wave Computing nanoMIPS */
--- a/target/rx/insns.decode
+++ b/target/rx/insns.decode
@ -7,7 +7,7 @@
 # This library is free software; you can redistribute it and/or
 # modify it under the terms of the GNU Lesser General Public
 # License as published by the Free Software Foundation; either
-# version 2 of the License, or (at your option) any later version.
+# version 2.1 of the License, or (at your option) any later version.
 #
 # This library is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz)
    env->psw_c = (tmp <= env->regs[2]);
 }

-/* accumlator operations */
+/* accumulator operations */
 void helper_rmpa(CPURXState *env, uint32_t sz)
 {
    uint64_t result_l, prev;
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
    tcg_gen_xor_i32(temp, arg1, arg2);
    tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
    tcg_temp_free_i32(temp);
-    /* CMP not requred return */
+    /* CMP not required return */
    if (ret) {
        tcg_gen_mov_i32(ret, cpu_psw_s);
    }
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@ -160,7 +160,7 @@ typedef struct CPUSH4State {
    uint32_t pteh;		/* page table entry high register */
    uint32_t ptel;		/* page table entry low register */
    uint32_t ptea;		/* page table entry assistance register */
-    uint32_t ttb;		/* tranlation table base register */
+    uint32_t ttb;               /* translation table base register */
    uint32_t tea;		/* TLB exception address register */
    uint32_t tra;		/* TRAPA exception register */
    uint32_t expevt;		/* exception event register */
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@ -398,9 +398,11 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
    /* "Approximate" 1/sqrt(x) via actual computation.  */
    t0 = float32_sqrt(t0, &env->fp_status);
    t0 = float32_div(float32_one, t0, &env->fp_status);
-    /* Since this is supposed to be an approximation, an imprecision
-       exception is required.  One supposes this also follows the usual
-       IEEE rule that other exceptions take precidence.  */
+    /*
+     * Since this is supposed to be an approximation, an imprecision
+     * exception is required.  One supposes this also follows the usual
+     * IEEE rule that other exceptions take precedence.
+     */
    if (get_float_exception_flags(&env->fp_status) == 0) {
        set_float_exception_flags(float_flag_inexact, &env->fp_status);
    }
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@ -1959,9 +1959,11 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
    NEXT_INSN;
    switch (ctx->opcode & 0xf00f) {
    case 0x6003: /* mov Rm,Rn */
-        /* Here we want to recognize ld_dst being saved for later consumtion,
-           or for another input register being copied so that ld_dst need not
-           be clobbered during the operation.  */
+        /*
+         * Here we want to recognize ld_dst being saved for later consumption,
+         * or for another input register being copied so that ld_dst need not
+         * be clobbered during the operation.
+         */
        op_dst = B11_8;
        mv_src = B7_4;
        if (op_dst == ld_dst) {