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target/arm: refactor vae1_tlbmask()
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-19-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4470,26 +4470,23 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
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static int vae1_tlbmask(CPUARMState *env)
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{
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uint64_t hcr = arm_hcr_el2_eff(env);
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uint16_t mask;
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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uint16_t mask = ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E20_0;
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if (arm_is_secure_below_el3(env)) {
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mask >>= ARM_MMU_IDX_A_NS;
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}
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return mask;
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} else if (arm_is_secure_below_el3(env)) {
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return ARMMMUIdxBit_SE10_1 |
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ARMMMUIdxBit_SE10_1_PAN |
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ARMMMUIdxBit_SE10_0;
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mask = ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E20_0;
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} else {
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return ARMMMUIdxBit_E10_1 |
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mask = ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0;
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}
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if (arm_is_secure_below_el3(env)) {
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mask >>= ARM_MMU_IDX_A_NS;
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}
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return mask;
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}
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/* Return 56 if TBI is enabled, 64 otherwise. */
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