From bfefe406b7666bfc624bf54820aa14bd43838dc5 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Tue, 18 Jan 2022 09:45:13 +0800 Subject: [PATCH] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-11-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cdb893d601..4f3d733db4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -688,6 +688,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), + DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),