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Extend TB flags to 64 bits (Alexander Graf).

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3198 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-09-20 22:47:42 +00:00
parent 5e3b100b65
commit c068688b03
4 changed files with 7 additions and 6 deletions
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4
cpu-exec.c
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@ -77,7 +77,7 @@ void cpu_resume_from_signal(CPUState *env1, void *puc)
static TranslationBlock *tb_find_slow(target_ulong pc,
target_ulong cs_base,
unsigned int flags)
uint64_t flags)
{
TranslationBlock *tb, **ptb1;
int code_gen_size;
@ -155,7 +155,7 @@ static inline TranslationBlock *tb_find_fast(void)
{
TranslationBlock *tb;
target_ulong cs_base, pc;
unsigned int flags;
uint64_t flags;
/* we record a subset of the CPU state. It will
always be the same before a given translated block

2
exec-all.h
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@ -171,7 +171,7 @@ static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
typedef struct TranslationBlock {
target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
target_ulong cs_base; /* CS base for this block */
unsigned int flags; /* flags defining in which context the code was generated */
uint64_t flags; /* flags defining in which context the code was generated */
uint16_t size; /* size of target code for this block (1 <=
size <= TARGET_PAGE_SIZE) */
uint16_t cflags; /* compile flags */

5
target-i386/translate.c
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@ -95,7 +95,7 @@ typedef struct DisasContext {
int singlestep_enabled; /* "hardware" single step enabled */
int jmp_opt; /* use direct block chaining for direct jumps */
int mem_index; /* select memory access functions */
int flags; /* all execution flags */
uint64_t flags; /* all execution flags */
struct TranslationBlock *tb;
int popl_esp_hack; /* for correct popl with esp base handling */
int rip_offset; /* only used in x86_64, but left for simplicity */
@ -6462,7 +6462,8 @@ static inline int gen_intermediate_code_internal(CPUState *env,
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
uint16_t *gen_opc_end;
int flags, j, lj, cflags;
int j, lj, cflags;
uint64_t flags;
target_ulong pc_start;
target_ulong cs_base;

2
target-mips/translate.c
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@ -6403,7 +6403,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
ctx.tb = tb;
ctx.bstate = BS_NONE;
/* Restore delay slot state from the tb context. */
ctx.hflags = tb->flags;
ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
restore_cpu_state(env, &ctx);
#if defined(CONFIG_USER_ONLY)
ctx.mem_idx = 0;