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s390x/tcg: Implement VECTOR AVERAGE
Handle 32/64-bit elements via gvec expansion and the 8/16 bits via ool helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
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@ -1,7 +1,7 @@
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obj-y += cpu.o cpu_models.o cpu_features.o gdbstub.o interrupt.o helper.o
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obj-$(CONFIG_TCG) += translate.o cc_helper.o excp_helper.o fpu_helper.o
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obj-$(CONFIG_TCG) += int_helper.o mem_helper.o misc_helper.o crypto_helper.o
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obj-$(CONFIG_TCG) += vec_helper.o
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obj-$(CONFIG_TCG) += vec_helper.o vec_int_helper.o
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obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o arch_dump.o mmu_helper.o diag.o
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obj-$(CONFIG_SOFTMMU) += sigp.o
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obj-$(CONFIG_KVM) += kvm.o
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@ -145,6 +145,10 @@ DEF_HELPER_5(gvec_vpkls_cc64, void, ptr, cptr, cptr, env, i32)
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DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)
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/* === Vector Integer Instructions === */
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DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vavg16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_3(servc, i32, env, i64, i64)
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DEF_HELPER_4(diag, void, env, i32, i32, i32)
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@ -1068,6 +1068,8 @@
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F(0xe768, VN, VRR_c, V, 0, 0, 0, 0, vn, 0, IF_VEC)
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/* VECTOR AND WITH COMPLEMENT */
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F(0xe769, VNC, VRR_c, V, 0, 0, 0, 0, vnc, 0, IF_VEC)
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/* VECTOR AVERAGE */
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F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
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#ifndef CONFIG_USER_ONLY
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/* COMPARE AND SWAP AND PURGE */
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@ -256,6 +256,17 @@ static void zero_vec(uint8_t reg)
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tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
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}
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static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
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uint64_t b)
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{
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TCGv_i64 bl = tcg_const_i64(b);
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TCGv_i64 bh = tcg_const_i64(0);
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tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
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tcg_temp_free_i64(bl);
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tcg_temp_free_i64(bh);
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}
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static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = s->insn->data;
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@ -1192,3 +1203,56 @@ static DisasJumpType op_vnc(DisasContext *s, DisasOps *o)
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get_field(s->fields, v2), get_field(s->fields, v3));
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return DISAS_NEXT;
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}
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static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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tcg_gen_ext_i32_i64(t0, a);
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tcg_gen_ext_i32_i64(t1, b);
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tcg_gen_add_i64(t0, t0, t1);
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tcg_gen_addi_i64(t0, t0, 1);
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tcg_gen_shri_i64(t0, t0, 1);
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tcg_gen_extrl_i64_i32(d, t0);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
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{
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TCGv_i64 dh = tcg_temp_new_i64();
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TCGv_i64 ah = tcg_temp_new_i64();
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TCGv_i64 bh = tcg_temp_new_i64();
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/* extending the sign by one bit is sufficient */
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tcg_gen_extract_i64(ah, al, 63, 1);
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tcg_gen_extract_i64(bh, bl, 63, 1);
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tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
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gen_addi2_i64(dl, dh, dl, dh, 1);
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tcg_gen_extract2_i64(dl, dl, dh, 1);
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tcg_temp_free_i64(dh);
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tcg_temp_free_i64(ah);
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tcg_temp_free_i64(bh);
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}
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static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = get_field(s->fields, m4);
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static const GVecGen3 g[4] = {
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{ .fno = gen_helper_gvec_vavg8, },
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{ .fno = gen_helper_gvec_vavg16, },
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{ .fni4 = gen_avg_i32, },
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{ .fni8 = gen_avg_i64, },
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};
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if (es > ES_64) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
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get_field(s->fields, v3), &g[es]);
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return DISAS_NEXT;
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}
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32
target/s390x/vec_int_helper.c
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32
target/s390x/vec_int_helper.c
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@ -0,0 +1,32 @@
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/*
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* QEMU TCG support -- s390x vector integer instruction support
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*
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* Copyright (C) 2019 Red Hat Inc
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*
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* Authors:
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* David Hildenbrand <david@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "vec.h"
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#include "exec/helper-proto.h"
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#define DEF_VAVG(BITS) \
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void HELPER(gvec_vavg##BITS)(void *v1, const void *v2, const void *v3, \
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uint32_t desc) \
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{ \
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int i; \
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\
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for (i = 0; i < (128 / BITS); i++) { \
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const int32_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, i); \
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const int32_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, i); \
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\
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s390_vec_write_element##BITS(v1, i, (a + b + 1) >> 1); \
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} \
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}
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DEF_VAVG(8)
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DEF_VAVG(16)
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