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hw/mips: Add CPU IRQ3 delivery for KVM

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Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add
IP3 delivery as well, because Loongson-3 based machine use both IRQ2
(CPU's IP2) and IRQ3 (CPU's IP3).

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1588501221-1205-4-git-send-email-chenhc@lemote.com>
This commit is contained in:
Huacai Chen 2020-05-03 18:20:17 +08:00 committed by Aleksandar Markovic
parent aa2953fd16
commit c3173a35bc
1 changed files with 1 additions and 1 deletions
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2
hw/mips/mips_int.c
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@ -51,7 +51,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
}
if (kvm_enabled() && irq == 2) {
if (kvm_enabled() && (irq == 2 || irq == 3)) {
kvm_mips_set_interrupt(cpu, irq, level);
}