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https://github.com/xemu-project/xemu.git
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openpic: merge mpic and openpic timer handling
The openpic and mpic timer handling code is basically the same. Merge them. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
5861a33898
commit
c38c0b8ad0
131
hw/openpic.c
131
hw/openpic.c
@ -195,7 +195,6 @@ enum IPVP_bits {
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#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
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typedef struct IRQ_dst_t {
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uint32_t tfrr;
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uint32_t pctp; /* CPU current task priority */
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uint32_t pcsr; /* CPU sensitivity register */
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IRQ_queue_t raised;
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@ -533,9 +532,6 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
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case 0x10E0: /* SPVE */
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opp->spve = val & 0x000000FF;
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break;
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case 0x10F0: /* TIFR */
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opp->tifr = val;
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break;
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default:
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break;
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}
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@ -587,9 +583,6 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
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case 0x10E0: /* SPVE */
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retval = opp->spve;
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break;
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case 0x10F0: /* TIFR */
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retval = opp->tifr;
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break;
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default:
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break;
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}
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@ -607,24 +600,28 @@ static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
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DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
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if (addr & 0xF)
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return;
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addr -= 0x10;
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addr &= 0xFFFF;
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idx = (addr & 0xFFF0) >> 6;
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idx = (addr >> 6) & 0x3;
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addr = addr & 0x30;
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switch (addr) {
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case 0x00: /* TICC */
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if (addr == 0x0) {
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/* TIFR (TFRR) */
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opp->tifr = val;
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return;
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}
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switch (addr & 0x30) {
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case 0x00: /* TICC (GTCCR) */
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break;
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case 0x10: /* TIBC */
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case 0x10: /* TIBC (GTBCR) */
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if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
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(val & 0x80000000) == 0 &&
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(opp->timers[idx].tibc & 0x80000000) != 0)
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opp->timers[idx].ticc &= ~0x80000000;
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opp->timers[idx].tibc = val;
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break;
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case 0x20: /* TIVP */
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case 0x20: /* TIVP (GTIVPR) */
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write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val);
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break;
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case 0x30: /* TIDE */
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case 0x30: /* TIDE (GTIDR) */
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write_IRQreg_ide(opp, opp->irq_tim0 + idx, val);
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break;
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}
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@ -633,31 +630,35 @@ static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
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static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
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{
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openpic_t *opp = opaque;
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uint32_t retval;
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uint32_t retval = -1;
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int idx;
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DPRINTF("%s: addr %08x\n", __func__, addr);
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retval = 0xFFFFFFFF;
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if (addr & 0xF)
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return retval;
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addr -= 0x10;
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addr &= 0xFFFF;
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idx = (addr & 0xFFF0) >> 6;
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addr = addr & 0x30;
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switch (addr) {
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case 0x00: /* TICC */
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if (addr & 0xF) {
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goto out;
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}
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idx = (addr >> 6) & 0x3;
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if (addr == 0x0) {
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/* TIFR (TFRR) */
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retval = opp->tifr;
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goto out;
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}
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switch (addr & 0x30) {
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case 0x00: /* TICC (GTCCR) */
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retval = opp->timers[idx].ticc;
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break;
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case 0x10: /* TIBC */
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case 0x10: /* TIBC (GTBCR) */
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retval = opp->timers[idx].tibc;
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break;
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case 0x20: /* TIPV */
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case 0x20: /* TIPV (TIPV) */
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retval = read_IRQreg_ipvp(opp, opp->irq_tim0 + idx);
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break;
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case 0x30: /* TIDE */
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case 0x30: /* TIDE (TIDR) */
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retval = read_IRQreg_ide(opp, opp->irq_tim0 + idx);
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break;
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}
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out:
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DPRINTF("%s: => %08x\n", __func__, retval);
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return retval;
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@ -930,7 +931,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
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qemu_put_sbe32s(f, &opp->nb_cpus);
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for (i = 0; i < opp->nb_cpus; i++) {
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qemu_put_be32s(f, &opp->dst[i].tfrr);
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qemu_put_be32s(f, &opp->dst[i].pctp);
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qemu_put_be32s(f, &opp->dst[i].pcsr);
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openpic_save_IRQ_queue(f, &opp->dst[i].raised);
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@ -983,7 +983,6 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
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qemu_get_sbe32s(f, &opp->nb_cpus);
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for (i = 0; i < opp->nb_cpus; i++) {
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qemu_get_be32s(f, &opp->dst[i].tfrr);
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qemu_get_be32s(f, &opp->dst[i].pctp);
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qemu_get_be32s(f, &opp->dst[i].pcsr);
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openpic_load_IRQ_queue(f, &opp->dst[i].raised);
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@ -1100,7 +1099,6 @@ static void mpic_reset (void *opaque)
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/* Initialise IRQ destinations */
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for (i = 0; i < MAX_CPU; i++) {
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mpp->dst[i].pctp = 0x0000000F;
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mpp->dst[i].tfrr = 0x00000000;
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memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t));
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mpp->dst[i].raised.next = -1;
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memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
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@ -1115,73 +1113,6 @@ static void mpic_reset (void *opaque)
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mpp->glbc = 0x00000000;
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}
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static void mpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_t *mpp = opaque;
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int idx, cpu;
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DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
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if (addr & 0xF)
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return;
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cpu = addr >> 12;
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idx = (addr >> 6) & 0x3;
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switch (addr & 0x30) {
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case 0x00: /* gtccr */
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break;
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case 0x10: /* gtbcr */
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if ((mpp->timers[idx].ticc & 0x80000000) != 0 &&
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(val & 0x80000000) == 0 &&
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(mpp->timers[idx].tibc & 0x80000000) != 0)
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mpp->timers[idx].ticc &= ~0x80000000;
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mpp->timers[idx].tibc = val;
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break;
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case 0x20: /* GTIVPR */
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write_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx, val);
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break;
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case 0x30: /* GTIDR & TFRR */
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if ((addr & 0xF0) == 0xF0)
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mpp->dst[cpu].tfrr = val;
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else
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write_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx, val);
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break;
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}
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}
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static uint64_t mpic_timer_read(void *opaque, hwaddr addr, unsigned len)
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{
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openpic_t *mpp = opaque;
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uint32_t retval;
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int idx, cpu;
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DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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retval = 0xFFFFFFFF;
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if (addr & 0xF)
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return retval;
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cpu = addr >> 12;
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idx = (addr >> 6) & 0x3;
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switch (addr & 0x30) {
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case 0x00: /* gtccr */
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retval = mpp->timers[idx].ticc;
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break;
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case 0x10: /* gtbcr */
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retval = mpp->timers[idx].tibc;
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break;
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case 0x20: /* TIPV */
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retval = read_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx);
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break;
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case 0x30: /* TIDR */
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if ((addr &0xF0) == 0XF0)
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retval = mpp->dst[cpu].tfrr;
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else
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retval = read_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx);
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break;
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}
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DPRINTF("%s: => %08x\n", __func__, retval);
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return retval;
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}
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static const MemoryRegionOps mpic_glb_ops = {
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.write = openpic_gbl_write,
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.read = openpic_gbl_read,
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@ -1193,8 +1124,8 @@ static const MemoryRegionOps mpic_glb_ops = {
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};
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static const MemoryRegionOps mpic_tmr_ops = {
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.write = mpic_timer_write,
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.read = mpic_timer_read,
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.write = openpic_timer_write,
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.read = openpic_timer_read,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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