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target/riscv: debug: Add initial support of type 6 trigger
Type 6 trigger is similar to a type 2 trigger, but provides additional functionality and should be used instead of type 2 in newer implementations. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220909134215.1843865-9-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang
Alistair Francis
parent
c32461d8ee
commit
c472c142a7
@ -39,7 +39,7 @@
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* - tdata3
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* - tinfo
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*
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* The following triggers are implemented:
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* The following triggers are initialized by default:
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*
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* Index | Type | tdata mapping | Description
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* ------+------+------------------------+------------
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@ -103,10 +103,12 @@ static trigger_action_t get_trigger_action(CPURISCVState *env,
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case TRIGGER_TYPE_AD_MATCH:
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action = (tdata1 & TYPE2_ACTION) >> 12;
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break;
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case TRIGGER_TYPE_AD_MATCH6:
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action = (tdata1 & TYPE6_ACTION) >> 12;
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break;
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case TRIGGER_TYPE_INST_CNT:
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case TRIGGER_TYPE_INT:
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case TRIGGER_TYPE_EXCP:
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case TRIGGER_TYPE_AD_MATCH6:
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case TRIGGER_TYPE_EXT_SRC:
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qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
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trigger_type);
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@ -379,6 +381,123 @@ static void type2_reg_write(CPURISCVState *env, target_ulong index,
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return;
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}
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/* type 6 trigger */
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static inline bool type6_breakpoint_enabled(target_ulong ctrl)
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{
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bool mode = !!(ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M));
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bool rwx = !!(ctrl & (TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC));
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return mode && rwx;
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}
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static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
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target_ulong ctrl)
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{
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target_ulong val;
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uint32_t size;
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/* validate the generic part first */
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val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6);
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/* validate unimplemented (always zero) bits */
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warn_always_zero_bit(ctrl, TYPE6_MATCH, "match");
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warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain");
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warn_always_zero_bit(ctrl, TYPE6_ACTION, "action");
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warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
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warn_always_zero_bit(ctrl, TYPE6_SELECT, "select");
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warn_always_zero_bit(ctrl, TYPE6_HIT, "hit");
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/* validate size encoding */
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size = extract32(ctrl, 16, 4);
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if (access_size[size] == -1) {
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qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
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size);
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} else {
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val |= (ctrl & TYPE6_SIZE);
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}
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/* keep the mode and attribute bits */
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val |= (ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M |
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TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC));
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return val;
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}
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static void type6_breakpoint_insert(CPURISCVState *env, target_ulong index)
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{
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target_ulong ctrl = env->tdata1[index];
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target_ulong addr = env->tdata2[index];
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bool enabled = type6_breakpoint_enabled(ctrl);
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CPUState *cs = env_cpu(env);
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int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
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uint32_t size;
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if (!enabled) {
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return;
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}
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if (ctrl & TYPE6_EXEC) {
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cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]);
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}
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if (ctrl & TYPE6_LOAD) {
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flags |= BP_MEM_READ;
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}
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if (ctrl & TYPE6_STORE) {
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flags |= BP_MEM_WRITE;
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}
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if (flags & BP_MEM_ACCESS) {
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size = extract32(ctrl, 16, 4);
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if (size != 0) {
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cpu_watchpoint_insert(cs, addr, size, flags,
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&env->cpu_watchpoint[index]);
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} else {
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cpu_watchpoint_insert(cs, addr, 8, flags,
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&env->cpu_watchpoint[index]);
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}
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}
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}
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static void type6_breakpoint_remove(CPURISCVState *env, target_ulong index)
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{
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type2_breakpoint_remove(env, index);
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}
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static void type6_reg_write(CPURISCVState *env, target_ulong index,
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int tdata_index, target_ulong val)
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{
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target_ulong new_val;
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switch (tdata_index) {
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case TDATA1:
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new_val = type6_mcontrol6_validate(env, val);
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if (new_val != env->tdata1[index]) {
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env->tdata1[index] = new_val;
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type6_breakpoint_remove(env, index);
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type6_breakpoint_insert(env, index);
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}
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break;
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case TDATA2:
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if (val != env->tdata2[index]) {
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env->tdata2[index] = val;
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type6_breakpoint_remove(env, index);
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type6_breakpoint_insert(env, index);
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}
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break;
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case TDATA3:
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qemu_log_mask(LOG_UNIMP,
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"tdata3 is not supported for type 6 trigger\n");
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break;
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default:
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g_assert_not_reached();
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}
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return;
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}
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target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
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{
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switch (tdata_index) {
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@ -407,10 +526,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
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case TRIGGER_TYPE_AD_MATCH:
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type2_reg_write(env, env->trigger_cur, tdata_index, val);
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break;
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case TRIGGER_TYPE_AD_MATCH6:
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type6_reg_write(env, env->trigger_cur, tdata_index, val);
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break;
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case TRIGGER_TYPE_INST_CNT:
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case TRIGGER_TYPE_INT:
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case TRIGGER_TYPE_EXCP:
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case TRIGGER_TYPE_AD_MATCH6:
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case TRIGGER_TYPE_EXT_SRC:
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qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
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trigger_type);
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@ -428,7 +549,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
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target_ulong tinfo_csr_read(CPURISCVState *env)
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{
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/* assume all triggers support the same types of triggers */
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return BIT(TRIGGER_TYPE_AD_MATCH);
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return BIT(TRIGGER_TYPE_AD_MATCH) |
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BIT(TRIGGER_TYPE_AD_MATCH6);
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}
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void riscv_cpu_debug_excp_handler(CPUState *cs)
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@ -479,6 +601,24 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
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}
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}
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break;
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case TRIGGER_TYPE_AD_MATCH6:
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ctrl = env->tdata1[i];
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pc = env->tdata2[i];
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if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
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if (riscv_cpu_virt_enabled(env)) {
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/* check VU/VS bit against current privilege level */
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if ((ctrl >> 23) & BIT(env->priv)) {
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return true;
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}
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} else {
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/* check U/S/M bit against current privilege level */
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if ((ctrl >> 3) & BIT(env->priv)) {
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return true;
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}
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}
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}
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break;
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default:
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/* other trigger types are not supported or irrelevant */
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break;
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@ -527,6 +667,32 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
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}
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}
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break;
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case TRIGGER_TYPE_AD_MATCH6:
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ctrl = env->tdata1[i];
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addr = env->tdata2[i];
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flags = 0;
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if (ctrl & TYPE6_LOAD) {
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flags |= BP_MEM_READ;
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}
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if (ctrl & TYPE6_STORE) {
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flags |= BP_MEM_WRITE;
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}
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if ((wp->flags & flags) && (wp->vaddr == addr)) {
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if (riscv_cpu_virt_enabled(env)) {
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/* check VU/VS bit against current privilege level */
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if ((ctrl >> 23) & BIT(env->priv)) {
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return true;
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}
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} else {
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/* check U/S/M bit against current privilege level */
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if ((ctrl >> 3) & BIT(env->priv)) {
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return true;
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}
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}
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}
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break;
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default:
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/* other trigger types are not supported */
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break;
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@ -85,6 +85,24 @@ typedef enum {
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#define TYPE2_HIT BIT(20)
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#define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */
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/* mcontrol6 field masks */
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#define TYPE6_LOAD BIT(0)
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#define TYPE6_STORE BIT(1)
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#define TYPE6_EXEC BIT(2)
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#define TYPE6_U BIT(3)
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#define TYPE6_S BIT(4)
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#define TYPE6_M BIT(6)
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#define TYPE6_MATCH (0xf << 7)
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#define TYPE6_CHAIN BIT(11)
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#define TYPE6_ACTION (0xf << 12)
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#define TYPE6_SIZE (0xf << 16)
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#define TYPE6_TIMING BIT(20)
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#define TYPE6_SELECT BIT(21)
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#define TYPE6_HIT BIT(22)
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#define TYPE6_VU BIT(23)
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#define TYPE6_VS BIT(24)
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/* access size */
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enum {
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SIZE_ANY = 0,
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