xemu-project/xemu
1
0
Fork 0
mirror of https://github.com/xemu-project/xemu.git synced 2024-11-23 19:49:43 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

target-arm: Check undefined opcodes for SWP in A32 decoder

Browse Source 
Make sure we are not treating architecturally Undefined instructions
as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A
specification. Bits [21:20] must be zero for this to be a SWP or SWPB.
We also choose to UNDEF for the architecturally UNPREDICTABLE case of
bits [11:8] not being zero.

Signed-off-by: Onur Sahin <onursahin08@gmail.com>
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Onur Sahin 2018-04-10 13:02:24 +01:00 committed by Peter Maydell
parent 8720daad47
commit c4869ca630
1 changed files with 7 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
target/arm/translate.c
View File

@ -9237,11 +9237,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
}
tcg_temp_free_i32(addr);
} else {
} else if ((insn & 0x00300f00) == 0) {
/* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
* - SWP, SWPB
*/
TCGv taddr;
TCGMemOp opc = s->be_data;
/* SWP instruction */
rm = (insn) & 0xf;
if (insn & (1 << 22)) {
@ -9259,6 +9262,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
get_mem_index(s), opc);
tcg_temp_free(taddr);
store_reg(s, rd, tmp);
} else {
goto illegal_op;
}
}
} else {