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target/ppc: Use MO_ALIGN for EXIWX and ECOWX

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This avoids the need for gen_check_align entirely.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson 2018-06-26 09:19:18 -07:00 committed by David Gibson
parent 9deb041cbd
commit c674a9831e
1 changed files with 4 additions and 21 deletions
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25
target/ppc/translate.c
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@ -2388,23 +2388,6 @@ static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
}
}
static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
{
TCGLabel *l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv_i32 t1, t2;
tcg_gen_andi_tl(t0, EA, mask);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
gen_update_nip(ctx, ctx->base.pc_next - 4);
gen_helper_raise_exception_err(cpu_env, t1, t2);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
gen_set_label(l1);
tcg_temp_free(t0);
}
static inline void gen_align_no_le(DisasContext *ctx)
{
gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
@ -4706,8 +4689,8 @@ static void gen_eciwx(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_EXT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_check_align(ctx, t0, 0x03);
gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
DEF_MEMOP(MO_UL | MO_ALIGN));
tcg_temp_free(t0);
}
@ -4719,8 +4702,8 @@ static void gen_ecowx(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_EXT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_check_align(ctx, t0, 0x03);
gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
DEF_MEMOP(MO_UL | MO_ALIGN));
tcg_temp_free(t0);
}