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target-mips: DMA support for RC4030 chipset
Attached patch implements DMA support to RC4030 chipset and simplifies jazz IO part (at 0xf0000000), where registers contain 16 bit values. Config register has not a clear meaning (only one value is always valid, and sometimes another one), so use a magic value instead. The patch also wires DMA transfers for the SCSI adapter in the Jazz emulation (Mips Magnum 4000 and Acer Pica 61). Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6145 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
3aa9bd6c35
commit
c6945b153c
@ -27,6 +27,10 @@ extern void cpu_mips_irq_init_cpu(CPUState *env);
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extern void cpu_mips_clock_init(CPUState *);
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/* rc4030.c */
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qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus);
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typedef struct rc4030DMAState *rc4030_dma;
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typedef void (*rc4030_dma_function)(void *dma, uint8_t *buf, int len);
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qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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rc4030_dma **dmas,
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rc4030_dma_function *dma_read, rc4030_dma_function *dma_write);
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#endif
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@ -75,6 +75,24 @@ static CPUWriteMemoryFunc *rtc_write[3] = {
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rtc_writeb,
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};
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static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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/* Nothing to do. That is only to ensure that
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* the current DMA acknowledge cycle is completed. */
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}
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static CPUReadMemoryFunc *dma_dummy_read[3] = {
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NULL,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc *dma_dummy_write[3] = {
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dma_dummy_writeb,
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dma_dummy_writeb,
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dma_dummy_writeb,
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};
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#ifdef HAS_AUDIO
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static void audio_init(qemu_irq *pic)
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{
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@ -102,16 +120,6 @@ static void audio_init(qemu_irq *pic)
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}
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#endif
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static void espdma_memory_read(void *opaque, uint8_t *buf, int len)
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{
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printf("espdma_memory_read(buf %p, len %d) not implemented\n", buf, len);
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}
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static void espdma_memory_write(void *opaque, uint8_t *buf, int len)
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{
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printf("espdma_memory_write(buf %p, len %d) not implemented\n", buf, len);
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}
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#define MAGNUM_BIOS_SIZE_MAX 0x7e000
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#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
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@ -125,9 +133,11 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
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int bios_size, n;
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CPUState *env;
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qemu_irq *rc4030, *i8259;
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rc4030_dma *dmas;
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rc4030_dma_function dma_read, dma_write;
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void *scsi_hba;
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int hd;
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int s_rtc;
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int s_rtc, s_dma_dummy;
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PITState *pit;
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BlockDriverState *fds[MAX_FD];
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qemu_irq esp_reset;
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@ -153,7 +163,9 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
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/* load the BIOS image. */
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bios_offset = ram_size + vga_ram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
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fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
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@ -171,10 +183,14 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
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cpu_mips_clock_init(env);
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/* Chipset */
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rc4030 = rc4030_init(env->irq[6], env->irq[3]);
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rc4030 = rc4030_init(env->irq[6], env->irq[3],
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&dmas, &dma_read, &dma_write);
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s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL);
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cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
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/* ISA devices */
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i8259 = i8259_init(env->irq[4]);
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DMA_init(0);
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pit = pit_init(0x40, i8259[0]);
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pcspk_init(pit);
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@ -200,7 +216,7 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
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/* SCSI adapter */
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scsi_hba = esp_init(0x80002000, 0,
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espdma_memory_read, espdma_memory_write, NULL,
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dma_read, dma_write, dmas[0],
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rc4030[5], &esp_reset);
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for (n = 0; n < ESP_MAX_DEVS; n++) {
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hd = drive_get_index(IF_SCSI, 0, n);
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@ -278,6 +294,7 @@ QEMUMachine mips_magnum_machine = {
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.init = mips_magnum_init,
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.ram_require = MAGNUM_BIOS_SIZE + VGA_RAM_SIZE,
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.nodisk_ok = 1,
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.use_scsi = 1,
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};
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QEMUMachine mips_pica61_machine = {
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@ -286,4 +303,5 @@ QEMUMachine mips_pica61_machine = {
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.init = mips_pica61_init,
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.ram_require = MAGNUM_BIOS_SIZE + VGA_RAM_SIZE,
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.nodisk_ok = 1,
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.use_scsi = 1,
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};
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294
hw/rc4030.c
294
hw/rc4030.c
@ -26,13 +26,43 @@
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#include "mips.h"
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#include "qemu-timer.h"
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/********************************************************/
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/* debug rc4030 */
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//#define DEBUG_RC4030
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//#define DEBUG_RC4030_DMA
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#ifdef DEBUG_RC4030
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#define DPRINTF(fmt, args...) \
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do { printf("rc4030: " fmt , ##args); } while (0)
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static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
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"network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define RC4030_ERROR(fmt, args...) \
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do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ##args); } while (0)
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/********************************************************/
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/* rc4030 emulation */
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typedef struct dma_pagetable_entry {
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int32_t frame;
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int32_t owner;
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} __attribute__((packed)) dma_pagetable_entry;
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#define DMA_PAGESIZE 4096
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#define DMA_REG_ENABLE 1
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#define DMA_REG_COUNT 2
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#define DMA_REG_ADDRESS 3
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#define DMA_FLAG_ENABLE 0x0001
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#define DMA_FLAG_MEM_TO_DEV 0x0002
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#define DMA_FLAG_TC_INTR 0x0100
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#define DMA_FLAG_MEM_INTR 0x0200
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#define DMA_FLAG_ADDR_INTR 0x0400
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typedef struct rc4030State
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{
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uint32_t config; /* 0x0000: RC4030 config register */
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@ -51,7 +81,6 @@ typedef struct rc4030State
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uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
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uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */
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uint32_t offset208;
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uint32_t offset210;
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uint32_t nvram_protect; /* 0x0220: NV ram protect register */
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uint32_t offset238;
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@ -63,7 +92,6 @@ typedef struct rc4030State
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QEMUTimer *periodic_timer;
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uint32_t itr; /* Interval timer reload */
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uint32_t dummy32;
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qemu_irq timer_irq;
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qemu_irq jazz_bus_irq;
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} rc4030State;
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@ -165,7 +193,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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case 0x01d0:
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case 0x01d8:
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case 0x01e0:
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case 0x1e8:
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case 0x01e8:
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case 0x01f0:
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case 0x01f8:
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{
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@ -176,7 +204,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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break;
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/* Offset 0x0208 */
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case 0x0208:
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val = s->offset208;
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val = 0;
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break;
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/* Offset 0x0210 */
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case 0x0210:
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@ -188,7 +216,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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break;
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/* Interval timer count */
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case 0x0230:
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val = s->dummy32;
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val = 0;
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qemu_irq_lower(s->timer_irq);
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break;
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/* Offset 0x0238 */
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@ -196,17 +224,13 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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val = s->offset238;
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break;
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default:
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#ifdef DEBUG_RC4030
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printf("rc4030: invalid read [" TARGET_FMT_lx "]\n", addr);
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#endif
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RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr);
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val = 0;
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break;
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}
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#ifdef DEBUG_RC4030
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if ((addr & ~3) != 0x230)
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printf("rc4030: read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
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#endif
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DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr);
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return val;
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}
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@ -231,9 +255,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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rc4030State *s = opaque;
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addr &= 0x3fff;
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#ifdef DEBUG_RC4030
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printf("rc4030: write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
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#endif
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DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr);
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switch (addr & ~0x3) {
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/* Global config register */
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@ -248,6 +270,13 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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case 0x0020:
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s->dma_tl_limit = val;
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break;
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/* DMA transl. table invalidated */
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case 0x0028:
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break;
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/* Cache Maintenance */
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case 0x0030:
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RC4030_ERROR("Cache maintenance not handled yet (val 0x%02x)\n", val);
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break;
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/* I/O Cache Physical Tag */
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case 0x0048:
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s->cache_ptag = val;
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@ -322,7 +351,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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case 0x01d0:
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case 0x01d8:
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case 0x01e0:
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case 0x1e8:
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case 0x01e8:
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case 0x01f0:
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case 0x01f8:
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{
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@ -342,9 +371,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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set_next_tick(s);
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break;
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default:
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#ifdef DEBUG_RC4030
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printf("rc4030: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
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#endif
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RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr);
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break;
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}
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}
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@ -402,7 +429,7 @@ static void update_jazz_irq(rc4030State *s)
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#ifdef DEBUG_RC4030
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if (s->isr_jazz != 0) {
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uint32_t irq = 0;
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printf("jazz pending:");
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DPRINTF("pending irqs:");
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for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) {
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if (s->isr_jazz & (1 << irq)) {
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printf(" %s", irq_names[irq]);
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@ -442,7 +469,7 @@ static void rc4030_periodic_timer(void *opaque)
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qemu_irq_raise(s->timer_irq);
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}
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static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
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static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
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{
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rc4030State *s = opaque;
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uint32_t val;
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@ -450,14 +477,14 @@ static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
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addr &= 0xfff;
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switch (addr) {
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/* Local bus int source */
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case 0x00: {
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/* Local bus int source */
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uint32_t pending = s->isr_jazz & s->imr_jazz;
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val = 0;
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irq = 0;
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while (pending) {
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if (pending & 1) {
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//printf("returning irq %s\n", irq_names[irq]);
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DPRINTF("returning irq %s\n", irq_names[irq]);
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val = (irq + 1) << 2;
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break;
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}
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@ -466,100 +493,93 @@ static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
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}
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break;
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}
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/* Local bus int enable mask */
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case 0x02:
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val = s->imr_jazz;
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break;
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default:
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#ifdef DEBUG_RC4030
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printf("rc4030: (interrupt controller) invalid read [" TARGET_FMT_lx "]\n", addr);
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#endif
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val = 0;
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RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr);
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val = 0;
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}
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#ifdef DEBUG_RC4030
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printf("rc4030: (interrupt controller) read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
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#endif
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DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr);
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return val;
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}
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static uint32_t int_readw(void *opaque, target_phys_addr_t addr)
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static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v;
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v = int_readb(opaque, addr);
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v |= int_readb(opaque, addr + 1) << 8;
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v = jazzio_readw(opaque, addr & ~0x1);
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return (v >> (8 * (addr & 0x1))) & 0xff;
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}
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static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v;
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v = jazzio_readw(opaque, addr);
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v |= jazzio_readw(opaque, addr + 2) << 16;
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return v;
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}
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static uint32_t int_readl(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v;
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v = int_readb(opaque, addr);
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v |= int_readb(opaque, addr + 1) << 8;
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v |= int_readb(opaque, addr + 2) << 16;
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v |= int_readb(opaque, addr + 3) << 24;
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return v;
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}
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static void int_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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rc4030State *s = opaque;
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addr &= 0xfff;
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#ifdef DEBUG_RC4030
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printf("rc4030: (interrupt controller) write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
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#endif
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DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr);
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switch (addr) {
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/* Local bus int enable mask */
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case 0x02:
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s->imr_jazz = (s->imr_jazz & 0xff00) | (val << 0); update_jazz_irq(s);
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break;
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case 0x03:
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s->imr_jazz = (s->imr_jazz & 0x00ff) | (val << 8); update_jazz_irq(s);
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s->imr_jazz = val;
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update_jazz_irq(s);
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break;
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default:
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#ifdef DEBUG_RC4030
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printf("rc4030: (interrupt controller) invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
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#endif
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RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr);
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break;
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}
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}
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static void int_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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int_writeb(opaque, addr, val & 0xff);
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int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
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uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
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switch (addr & 1) {
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case 0:
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val = val | (old_val & 0xff00);
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break;
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case 1:
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val = (val << 8) | (old_val & 0x00ff);
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break;
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}
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jazzio_writew(opaque, addr & ~0x1, val);
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}
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static void int_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
|
||||
int_writeb(opaque, addr, val & 0xff);
|
||||
int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
||||
int_writeb(opaque, addr + 2, (val >> 16) & 0xff);
|
||||
int_writeb(opaque, addr + 3, (val >> 24) & 0xff);
|
||||
jazzio_writew(opaque, addr, val & 0xffff);
|
||||
jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc *int_read[3] = {
|
||||
int_readb,
|
||||
int_readw,
|
||||
int_readl,
|
||||
static CPUReadMemoryFunc *jazzio_read[3] = {
|
||||
jazzio_readb,
|
||||
jazzio_readw,
|
||||
jazzio_readl,
|
||||
};
|
||||
|
||||
static CPUWriteMemoryFunc *int_write[3] = {
|
||||
int_writeb,
|
||||
int_writew,
|
||||
int_writel,
|
||||
static CPUWriteMemoryFunc *jazzio_write[3] = {
|
||||
jazzio_writeb,
|
||||
jazzio_writew,
|
||||
jazzio_writel,
|
||||
};
|
||||
|
||||
#define G364_512KB_RAM (0x0)
|
||||
#define G364_2MB_RAM (0x1)
|
||||
#define G364_8MB_RAM (0x2)
|
||||
#define G364_32MB_RAM (0x3)
|
||||
|
||||
static void rc4030_reset(void *opaque)
|
||||
{
|
||||
rc4030State *s = opaque;
|
||||
int i;
|
||||
|
||||
s->config = (G364_2MB_RAM << 8) | 0x04;
|
||||
s->config = 0x410; /* some boards seem to accept 0x104 too */
|
||||
s->invalid_address_register = 0;
|
||||
|
||||
memset(s->dma_regs, 0, sizeof(s->dma_regs));
|
||||
@ -569,7 +589,6 @@ static void rc4030_reset(void *opaque)
|
||||
s->cache_ptag = s->cache_ltag = 0;
|
||||
s->cache_bmask = s->cache_bwin = 0;
|
||||
|
||||
s->offset208 = 0;
|
||||
s->offset210 = 0x18186;
|
||||
s->nvram_protect = 7;
|
||||
s->offset238 = 7;
|
||||
@ -578,21 +597,134 @@ static void rc4030_reset(void *opaque)
|
||||
s->imr_jazz = s->isr_jazz = 0;
|
||||
|
||||
s->itr = 0;
|
||||
s->dummy32 = 0;
|
||||
|
||||
qemu_irq_lower(s->timer_irq);
|
||||
qemu_irq_lower(s->jazz_bus_irq);
|
||||
}
|
||||
|
||||
qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus)
|
||||
static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
|
||||
{
|
||||
rc4030State *s = opaque;
|
||||
target_phys_addr_t entry_addr;
|
||||
target_phys_addr_t dma_addr, phys_addr;
|
||||
dma_pagetable_entry entry;
|
||||
int index, dev_to_mem;
|
||||
int ncpy, i;
|
||||
|
||||
s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
|
||||
|
||||
/* Check DMA channel consistency */
|
||||
dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
|
||||
if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
|
||||
(is_write != dev_to_mem)) {
|
||||
s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
|
||||
return;
|
||||
}
|
||||
|
||||
if (len > s->dma_regs[n][DMA_REG_COUNT])
|
||||
len = s->dma_regs[n][DMA_REG_COUNT];
|
||||
|
||||
dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
|
||||
i = 0;
|
||||
for (;;) {
|
||||
if (i == len) {
|
||||
s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
|
||||
break;
|
||||
}
|
||||
|
||||
ncpy = DMA_PAGESIZE - (dma_addr & (DMA_PAGESIZE - 1));
|
||||
if (ncpy > len - i)
|
||||
ncpy = len - i;
|
||||
|
||||
/* Get DMA translation table entry */
|
||||
index = dma_addr / DMA_PAGESIZE;
|
||||
if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
|
||||
s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
|
||||
break;
|
||||
}
|
||||
entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
|
||||
/* XXX: not sure. should we really use only lowest bits? */
|
||||
entry_addr &= 0x7fffffff;
|
||||
cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0);
|
||||
|
||||
/* Read/write data at right place */
|
||||
phys_addr = entry.frame + (dma_addr & (DMA_PAGESIZE - 1));
|
||||
cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
|
||||
|
||||
i += ncpy;
|
||||
dma_addr += ncpy;
|
||||
s->dma_regs[n][DMA_REG_COUNT] -= ncpy;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_RC4030_DMA
|
||||
{
|
||||
int i, j;
|
||||
printf("rc4030 dma: Copying %d bytes %s host %p\n",
|
||||
len, is_write ? "from" : "to", buf);
|
||||
for (i = 0; i < len; i += 16) {
|
||||
int n = min(16, len - i);
|
||||
for (j = 0; j < n; j++)
|
||||
printf("%02x ", buf[i + j]);
|
||||
while (j++ < 16)
|
||||
printf(" ");
|
||||
printf("| ");
|
||||
for (j = 0; j < n; j++)
|
||||
printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
struct rc4030DMAState {
|
||||
void *opaque;
|
||||
int n;
|
||||
};
|
||||
|
||||
static void rc4030_dma_read(void *dma, uint8_t *buf, int len)
|
||||
{
|
||||
rc4030_dma s = dma;
|
||||
rc4030_do_dma(s->opaque, s->n, buf, len, 0);
|
||||
}
|
||||
|
||||
static void rc4030_dma_write(void *dma, uint8_t *buf, int len)
|
||||
{
|
||||
rc4030_dma s = dma;
|
||||
rc4030_do_dma(s->opaque, s->n, buf, len, 1);
|
||||
}
|
||||
|
||||
static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
|
||||
{
|
||||
rc4030_dma *s;
|
||||
struct rc4030DMAState *p;
|
||||
int i;
|
||||
|
||||
s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
|
||||
p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n);
|
||||
for (i = 0; i < n; i++) {
|
||||
p->opaque = opaque;
|
||||
p->n = i;
|
||||
s[i] = p;
|
||||
p++;
|
||||
}
|
||||
return s;
|
||||
}
|
||||
|
||||
qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
|
||||
rc4030_dma **dmas,
|
||||
rc4030_dma_function *dma_read, rc4030_dma_function *dma_write)
|
||||
{
|
||||
rc4030State *s;
|
||||
int s_chipset, s_int;
|
||||
int s_chipset, s_jazzio;
|
||||
|
||||
s = qemu_mallocz(sizeof(rc4030State));
|
||||
if (!s)
|
||||
return NULL;
|
||||
|
||||
*dmas = rc4030_allocate_dmas(s, 4);
|
||||
*dma_read = rc4030_dma_read;
|
||||
*dma_write = rc4030_dma_write;
|
||||
|
||||
s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
|
||||
s->timer_irq = timer;
|
||||
s->jazz_bus_irq = jazz_bus;
|
||||
@ -602,8 +734,8 @@ qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus)
|
||||
|
||||
s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
|
||||
cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
|
||||
s_int = cpu_register_io_memory(0, int_read, int_write, s);
|
||||
cpu_register_physical_memory(0xf0000000, 0x00001000, s_int);
|
||||
s_jazzio = cpu_register_io_memory(0, jazzio_read, jazzio_write, s);
|
||||
cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
|
||||
|
||||
return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user