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trivial patches for 2014-03-27

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Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-03-27' into staging

trivial patches for 2014-03-27

# gpg: Signature made Thu 27 Mar 2014 15:23:53 GMT using RSA key ID 74F0C838
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>"
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>"
# gpg:                 aka "Michael Tokarev <mjt@debian.org>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D  4324 457C E0A0 8044 65C5
#      Subkey fingerprint: E190 8639 3B10 B51B AC2C  8B73 5253 C5AD 74F0 C838

* remotes/mjt/tags/trivial-patches-2014-03-27: (23 commits)
  linux-user: remove duplicate statement
  hw/timer/grlib_gptimer: remove unnecessary assignment
  hw/pci-host/apb.c: Avoid shifting left into sign bit
  hw/intc/xilinx_intc: Avoid shifting left into sign bit
  hw/intc/slavio_intctl: Avoid shifting left into sign bit
  tests/libqos/pci-pc: Avoid shifting left into sign bit
  hw/ppc: Avoid shifting left into sign bit
  hw/intc/openpic: Avoid shifting left into sign bit
  hw/usb/hcd-ohci.c: Avoid shifting left into sign bit
  target-mips: Avoid shifting left into sign bit
  hw/i386/acpi_build.c: Avoid shifting left into sign bit
  hw/pci/pci_host.c: Avoid shifting left into sign bit
  hw/intc/apic.c: Use uint32_t for mask word in foreach_apic
  target-i386: Avoid shifting left into sign bit
  CODING_STYLE: Section about mixed declarations
  doc: update default PowerPC framebuffer settings
  doc: update sun4m documentation
  fix return check for KVM_GET_DIRTY_LOG ioctl
  target-i386: Add missing 'static' and 'const' attributes
  util: Add 'static' attribute to function implementation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2014-03-27 16:38:58 +00:00
commit c6c09ba995
31 changed files with 271 additions and 256 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
CODING_STYLE
View File

@ -84,3 +84,10 @@ and clarity it comes on a line by itself:
Rationale: a consistent (except for functions...) bracing style reduces
ambiguity and avoids needless churn when lines are added or removed.
Furthermore, it is the QEMU coding style.
5. Declarations
Mixed declarations (interleaving statements and declarations within blocks)
are not allowed; declarations should be at the beginning of blocks. In other
words, the code should not generate warnings if using GCC's
-Wdeclaration-after-statement option.

2
hw/i386/acpi-build.c
View File

@ -907,7 +907,7 @@ static void build_pci_bus_end(PCIBus *bus, void *bus_state)
build_append_byte(notify, 0x7B); /* AndOp */
build_append_byte(notify, 0x68); /* Arg0Op */
build_append_int(notify, 0x1 << i);
build_append_int(notify, 0x1U << i);
build_append_byte(notify, 0x00); /* NullName */
build_append_byte(notify, 0x86); /* NotifyOp */
build_append_nameseg(notify, "S%.02X_", PCI_DEVFN(i, 0));

2
hw/ide/pci.c
View File

@ -421,7 +421,7 @@ static const VMStateDescription vmstate_bmdma_current = {
}
};
const VMStateDescription vmstate_bmdma_status = {
static const VMStateDescription vmstate_bmdma_status = {
.name ="ide bmdma/status",
.version_id = 1,
.minimum_version_id = 1,

6
hw/intc/apic.c
View File

@ -201,12 +201,12 @@ static void apic_external_nmi(APICCommonState *s)
#define foreach_apic(apic, deliver_bitmask, code) \
{\
int __i, __j, __mask;\
int __i, __j;\
for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
__mask = deliver_bitmask[__i];\
uint32_t __mask = deliver_bitmask[__i];\
if (__mask) {\
for(__j = 0; __j < 32; __j++) {\
if (__mask & (1 << __j)) {\
if (__mask & (1U << __j)) {\
apic = local_apics[__i * 32 + __j];\
if (apic) {\
code;\

14
hw/intc/openpic.c
View File

@ -123,7 +123,7 @@ static FslMpicInfo fsl_mpic_42 = {
#define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
#define IDR_EP_SHIFT 31
#define IDR_EP_MASK (1 << IDR_EP_SHIFT)
#define IDR_EP_MASK (1U << IDR_EP_SHIFT)
#define IDR_CI0_SHIFT 30
#define IDR_CI1_SHIFT 29
#define IDR_P1_SHIFT 1
@ -220,17 +220,17 @@ typedef struct IRQSource {
} IRQSource;
#define IVPR_MASK_SHIFT 31
#define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT)
#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
#define IVPR_ACTIVITY_SHIFT 30
#define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT)
#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
#define IVPR_MODE_SHIFT 29
#define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT)
#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
#define IVPR_POLARITY_SHIFT 23
#define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT)
#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
#define IVPR_SENSE_SHIFT 22
#define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT)
#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
#define IVPR_PRIORITY_MASK (0xF << 16)
#define IVPR_PRIORITY_MASK (0xFU << 16)
#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)

2
hw/intc/slavio_intctl.c
View File

@ -272,7 +272,7 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
CPU_IRQ_TIMER_IN;
if (i == s->target_cpu) {
for (j = 0; j < 32; j++) {
if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
if ((s->intregm_pending & (1U << j)) && intbit_to_level[j]) {
s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
}
}

3
hw/intc/xilinx_intc.c
View File

@ -71,8 +71,9 @@ static void update_irq(struct xlx_pic *p)
/* Update the vector register. */
for (i = 0; i < 32; i++) {
if (p->regs[R_IPR] & (1 << i))
if (p->regs[R_IPR] & (1U << i)) {
break;
}
}
if (i == 32)
i = ~0;

10
hw/pci-host/apb.c
View File

@ -58,11 +58,11 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#define PBM_PCI_IMR_MASK 0x7fffffff
#define PBM_PCI_IMR_ENABLED 0x80000000
#define POR (1 << 31)
#define SOFT_POR (1 << 30)
#define SOFT_XIR (1 << 29)
#define BTN_POR (1 << 28)
#define BTN_XIR (1 << 27)
#define POR (1U << 31)
#define SOFT_POR (1U << 30)
#define SOFT_XIR (1U << 29)
#define BTN_POR (1U << 28)
#define BTN_XIR (1U << 27)
#define RESET_MASK 0xf8000000
#define RESET_WCMASK 0x98000000
#define RESET_WMASK 0x60000000

3
hw/pci/pci_host.c
View File

@ -142,8 +142,9 @@ static uint64_t pci_host_data_read(void *opaque,
{
PCIHostState *s = opaque;
uint32_t val;
if (!(s->config_reg & (1 << 31)))
if (!(s->config_reg & (1U << 31))) {
return 0xffffffff;
}
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
addr, len, val);

2
hw/ppc/ppc.c
View File

@ -1002,7 +1002,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
case 0x1:
timer_mod(ppc40x_timer->wdt_timer, next);
ppc40x_timer->wdt_next = next;
env->spr[SPR_40x_TSR] |= 1 << 31;
env->spr[SPR_40x_TSR] |= 1U << 31;
break;
case 0x2:
timer_mod(ppc40x_timer->wdt_timer, next);

4
hw/ppc/ppc440_bamboo.c
View File

@ -128,7 +128,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env,
tlb->attr = 0;
tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
tlb->size = 1 << 31; /* up to 0x80000000 */
tlb->size = 1U << 31; /* up to 0x80000000 */
tlb->EPN = va & TARGET_PAGE_MASK;
tlb->RPN = pa & TARGET_PAGE_MASK;
tlb->PID = 0;
@ -136,7 +136,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env,
tlb = &env->tlb.tlbe[1];
tlb->attr = 0;
tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
tlb->size = 1 << 31; /* up to 0xffffffff */
tlb->size = 1U << 31; /* up to 0xffffffff */
tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
tlb->PID = 0;

2
hw/ppc/ppc4xx_devs.c
View File

@ -161,7 +161,7 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
uint32_t mask, sr;
uic = opaque;
mask = 1 << (31-irq_num);
mask = 1U << (31-irq_num);
LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
__func__, irq_num, level,

24
hw/ppc/ppc_booke.c
View File

@ -34,15 +34,15 @@
/* Timer Control Register */
#define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
#define TCR_WP_MASK (0x3 << TCR_WP_SHIFT)
#define TCR_WP_MASK (0x3U << TCR_WP_SHIFT)
#define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
#define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT)
#define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */
#define TCR_DIE (1 << 26) /* Decrementer Interrupt Enable */
#define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT)
#define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */
#define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */
#define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
#define TCR_FP_MASK (0x3 << TCR_FP_SHIFT)
#define TCR_FIE (1 << 23) /* Fixed-Interval Timer Interrupt Enable */
#define TCR_ARE (1 << 22) /* Auto-Reload Enable */
#define TCR_FP_MASK (0x3U << TCR_FP_SHIFT)
#define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
#define TCR_ARE (1U << 22) /* Auto-Reload Enable */
/* Timer Control Register (e500 specific fields) */
@ -53,12 +53,12 @@
/* Timer Status Register */
#define TSR_FIS (1 << 26) /* Fixed-Interval Timer Interrupt Status */
#define TSR_DIS (1 << 27) /* Decrementer Interrupt Status */
#define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */
#define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */
#define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
#define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT)
#define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */
#define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */
#define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT)
#define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */
#define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */
typedef struct booke_timer_t booke_timer_t;
struct booke_timer_t {

4
hw/ppc/virtex_ml507.c
View File

@ -71,7 +71,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env,
tlb->attr = 0;
tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
tlb->size = 1 << 31; /* up to 0x80000000 */
tlb->size = 1U << 31; /* up to 0x80000000 */
tlb->EPN = va & TARGET_PAGE_MASK;
tlb->RPN = pa & TARGET_PAGE_MASK;
tlb->PID = 0;
@ -79,7 +79,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env,
tlb = &env->tlb.tlbe[1];
tlb->attr = 0;
tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
tlb->size = 1 << 31; /* up to 0xffffffff */
tlb->size = 1U << 31; /* up to 0xffffffff */
tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
tlb->PID = 0;

1
hw/timer/grlib_gptimer.c
View File

@ -328,7 +328,6 @@ static void grlib_gptimer_reset(DeviceState *d)
unit->scaler = 0;
unit->reload = 0;
unit->config = 0;
unit->config = unit->nr_timers;
unit->config |= unit->irq_line << 3;

32
hw/usb/hcd-ohci.c
View File

@ -234,15 +234,15 @@ struct ohci_iso_td {
#define OHCI_STATUS_OCR (1<<3)
#define OHCI_STATUS_SOC ((1<<6)|(1<<7))
#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
#define OHCI_INTR_SF (1<<2) /* Start of frame */
#define OHCI_INTR_RD (1<<3) /* Resume detect */
#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
#define OHCI_INTR_OC (1<<30) /* Ownership change */
#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
#define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */
#define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */
#define OHCI_INTR_SF (1U<<2) /* Start of frame */
#define OHCI_INTR_RD (1U<<3) /* Resume detect */
#define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */
#define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */
#define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */
#define OHCI_INTR_OC (1U<<30) /* Ownership change */
#define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */
#define OHCI_HCCA_SIZE 0x100
#define OHCI_HCCA_MASK 0xffffff00
@ -253,7 +253,7 @@ struct ohci_iso_td {
#define OHCI_FMI_FSMPS 0xffff0000
#define OHCI_FMI_FIT 0x80000000
#define OHCI_FR_RT (1<<31)
#define OHCI_FR_RT (1U<<31)
#define OHCI_LS_THRESH 0x628
@ -265,12 +265,12 @@ struct ohci_iso_td {
#define OHCI_RHA_NOCP (1<<12)
#define OHCI_RHA_POTPGT_MASK 0xff000000
#define OHCI_RHS_LPS (1<<0)
#define OHCI_RHS_OCI (1<<1)
#define OHCI_RHS_DRWE (1<<15)
#define OHCI_RHS_LPSC (1<<16)
#define OHCI_RHS_OCIC (1<<17)
#define OHCI_RHS_CRWE (1<<31)
#define OHCI_RHS_LPS (1U<<0)
#define OHCI_RHS_OCI (1U<<1)
#define OHCI_RHS_DRWE (1U<<15)
#define OHCI_RHS_LPSC (1U<<16)
#define OHCI_RHS_OCIC (1U<<17)
#define OHCI_RHS_CRWE (1U<<31)
#define OHCI_PORT_CCS (1<<0)
#define OHCI_PORT_PES (1<<1)

2
kvm-all.c
View File

@ -441,7 +441,7 @@ static int kvm_physical_sync_dirty_bitmap(MemoryRegionSection *section)
d.slot = mem->slot;
if (kvm_vm_ioctl(s, KVM_GET_DIRTY_LOG, &d) == -1) {
if (kvm_vm_ioctl(s, KVM_GET_DIRTY_LOG, &d) < 0) {
DPRINTF("ioctl failed %d\n", errno);
ret = -1;
break;

2
linux-user/signal.c
View File

@ -4043,8 +4043,6 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka,
struct target_rt_sigframe *frame;
abi_ulong info_addr, uc_addr;
frame_addr = get_sigframe(ka, env, sizeof *frame);
frame_addr = get_sigframe(ka, env, sizeof(*frame));
if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
goto give_sigsegv;

11
qemu-doc.texi
View File

@ -1938,7 +1938,7 @@ The following options are specific to the PowerPC emulation:
@item -g @var{W}x@var{H}[x@var{DEPTH}]
Set the initial VGA graphic mode. The default is 800x600x15.
Set the initial VGA graphic mode. The default is 800x600x32.
@item -prom-env @var{string}
@ -1996,7 +1996,7 @@ QEMU emulates the following sun4m peripherals:
@item
IOMMU
@item
TCX Frame buffer
TCX or cgthree Frame buffer
@item
Lance (Am7990) Ethernet
@item
@ -2023,7 +2023,7 @@ firmware implementation. The goal is to implement a 100% IEEE
A sample Linux 2.6 series kernel and ram disk image are available on
the QEMU web site. There are still issues with NetBSD and OpenBSD, but
some kernel versions work. Please note that currently Solaris kernels
some kernel versions work. Please note that currently older Solaris kernels
don't work probably due to interface issues between OpenBIOS and
Solaris.
@ -2035,8 +2035,9 @@ The following options are specific to the Sparc32 emulation:
@item -g @var{W}x@var{H}x[x@var{DEPTH}]
Set the initial TCX graphic mode. The default is 1024x768x8, currently
the only other possible mode is 1024x768x24.
Set the initial graphics mode. For TCX, the default is 1024x768x8 with the
option of 1024x768x24. For cgthree, the default is 1024x768x8 with the option
of 1152x900x8 for people who wish to use OBP.
@item -prom-env @var{string}

10
qemu-options.hx
View File

@ -1043,7 +1043,7 @@ Rotate graphical output some deg left (only PXA LCD).
ETEXI
DEF("vga", HAS_ARG, QEMU_OPTION_vga,
"-vga [std|cirrus|vmware|qxl|xenfb|none]\n"
"-vga [std|cirrus|vmware|qxl|xenfb|tcx|cg3|none]\n"
" select video card type\n", QEMU_ARCH_ALL)
STEXI
@item -vga @var{type}
@ -1068,6 +1068,14 @@ card.
QXL paravirtual graphic card. It is VGA compatible (including VESA
2.0 VBE support). Works best with qxl guest drivers installed though.
Recommended choice when using the spice protocol.
@item tcx
(sun4m only) Sun TCX framebuffer. This is the default framebuffer for
sun4m machines and offers both 8-bit and 24-bit colour depths at a
fixed resolution of 1024x768.
@item cg3
(sun4m only) Sun cgthree framebuffer. This is a simple 8-bit framebuffer
for sun4m machines available in both 1024x768 (OpenBIOS) and 1152x900 (OBP)
resolutions aimed at people wishing to run older Solaris versions.
@item none
Disable VGA card.
@end table

2
target-arm/machine.c
View File

@ -88,7 +88,7 @@ static bool m_needed(void *opaque)
return arm_feature(env, ARM_FEATURE_M);
}
const VMStateDescription vmstate_m = {
static const VMStateDescription vmstate_m = {
.name = "cpu/m",
.version_id = 1,
.minimum_version_id = 1,

2
target-i386/cpu.c
View File

@ -316,7 +316,7 @@ typedef struct X86RegisterInfo32 {
#define REGISTER(reg) \
[R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
REGISTER(EAX),
REGISTER(ECX),
REGISTER(EDX),

324
target-i386/cpu.h
View File

@ -194,35 +194,35 @@
#define CR0_PE_SHIFT 0
#define CR0_MP_SHIFT 1
#define CR0_PE_MASK (1 << 0)
#define CR0_MP_MASK (1 << 1)
#define CR0_EM_MASK (1 << 2)
#define CR0_TS_MASK (1 << 3)
#define CR0_ET_MASK (1 << 4)
#define CR0_NE_MASK (1 << 5)
#define CR0_WP_MASK (1 << 16)
#define CR0_AM_MASK (1 << 18)
#define CR0_PG_MASK (1 << 31)
#define CR0_PE_MASK (1U << 0)
#define CR0_MP_MASK (1U << 1)
#define CR0_EM_MASK (1U << 2)
#define CR0_TS_MASK (1U << 3)
#define CR0_ET_MASK (1U << 4)
#define CR0_NE_MASK (1U << 5)
#define CR0_WP_MASK (1U << 16)
#define CR0_AM_MASK (1U << 18)
#define CR0_PG_MASK (1U << 31)
#define CR4_VME_MASK (1 << 0)
#define CR4_PVI_MASK (1 << 1)
#define CR4_TSD_MASK (1 << 2)
#define CR4_DE_MASK (1 << 3)
#define CR4_PSE_MASK (1 << 4)
#define CR4_PAE_MASK (1 << 5)
#define CR4_MCE_MASK (1 << 6)
#define CR4_PGE_MASK (1 << 7)
#define CR4_PCE_MASK (1 << 8)
#define CR4_VME_MASK (1U << 0)
#define CR4_PVI_MASK (1U << 1)
#define CR4_TSD_MASK (1U << 2)
#define CR4_DE_MASK (1U << 3)
#define CR4_PSE_MASK (1U << 4)
#define CR4_PAE_MASK (1U << 5)
#define CR4_MCE_MASK (1U << 6)
#define CR4_PGE_MASK (1U << 7)
#define CR4_PCE_MASK (1U << 8)
#define CR4_OSFXSR_SHIFT 9
#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
#define CR4_OSXMMEXCPT_MASK (1 << 10)
#define CR4_VMXE_MASK (1 << 13)
#define CR4_SMXE_MASK (1 << 14)
#define CR4_FSGSBASE_MASK (1 << 16)
#define CR4_PCIDE_MASK (1 << 17)
#define CR4_OSXSAVE_MASK (1 << 18)
#define CR4_SMEP_MASK (1 << 20)
#define CR4_SMAP_MASK (1 << 21)
#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
#define CR4_OSXMMEXCPT_MASK (1U << 10)
#define CR4_VMXE_MASK (1U << 13)
#define CR4_SMXE_MASK (1U << 14)
#define CR4_FSGSBASE_MASK (1U << 16)
#define CR4_PCIDE_MASK (1U << 17)
#define CR4_OSXSAVE_MASK (1U << 18)
#define CR4_SMEP_MASK (1U << 20)
#define CR4_SMAP_MASK (1U << 21)
#define DR6_BD (1 << 13)
#define DR6_BS (1 << 14)
@ -407,96 +407,96 @@ typedef enum FeatureWord {
typedef uint32_t FeatureWordArray[FEATURE_WORDS];
/* cpuid_features bits */
#define CPUID_FP87 (1 << 0)
#define CPUID_VME (1 << 1)
#define CPUID_DE (1 << 2)
#define CPUID_PSE (1 << 3)
#define CPUID_TSC (1 << 4)
#define CPUID_MSR (1 << 5)
#define CPUID_PAE (1 << 6)
#define CPUID_MCE (1 << 7)
#define CPUID_CX8 (1 << 8)
#define CPUID_APIC (1 << 9)
#define CPUID_SEP (1 << 11) /* sysenter/sysexit */
#define CPUID_MTRR (1 << 12)
#define CPUID_PGE (1 << 13)
#define CPUID_MCA (1 << 14)
#define CPUID_CMOV (1 << 15)
#define CPUID_PAT (1 << 16)
#define CPUID_PSE36 (1 << 17)
#define CPUID_PN (1 << 18)
#define CPUID_CLFLUSH (1 << 19)
#define CPUID_DTS (1 << 21)
#define CPUID_ACPI (1 << 22)
#define CPUID_MMX (1 << 23)
#define CPUID_FXSR (1 << 24)
#define CPUID_SSE (1 << 25)
#define CPUID_SSE2 (1 << 26)
#define CPUID_SS (1 << 27)
#define CPUID_HT (1 << 28)
#define CPUID_TM (1 << 29)
#define CPUID_IA64 (1 << 30)
#define CPUID_PBE (1 << 31)
#define CPUID_FP87 (1U << 0)
#define CPUID_VME (1U << 1)
#define CPUID_DE (1U << 2)
#define CPUID_PSE (1U << 3)
#define CPUID_TSC (1U << 4)
#define CPUID_MSR (1U << 5)
#define CPUID_PAE (1U << 6)
#define CPUID_MCE (1U << 7)
#define CPUID_CX8 (1U << 8)
#define CPUID_APIC (1U << 9)
#define CPUID_SEP (1U << 11) /* sysenter/sysexit */
#define CPUID_MTRR (1U << 12)
#define CPUID_PGE (1U << 13)
#define CPUID_MCA (1U << 14)
#define CPUID_CMOV (1U << 15)
#define CPUID_PAT (1U << 16)
#define CPUID_PSE36 (1U << 17)
#define CPUID_PN (1U << 18)
#define CPUID_CLFLUSH (1U << 19)
#define CPUID_DTS (1U << 21)
#define CPUID_ACPI (1U << 22)
#define CPUID_MMX (1U << 23)
#define CPUID_FXSR (1U << 24)
#define CPUID_SSE (1U << 25)
#define CPUID_SSE2 (1U << 26)
#define CPUID_SS (1U << 27)
#define CPUID_HT (1U << 28)
#define CPUID_TM (1U << 29)
#define CPUID_IA64 (1U << 30)
#define CPUID_PBE (1U << 31)
#define CPUID_EXT_SSE3 (1 << 0)
#define CPUID_EXT_PCLMULQDQ (1 << 1)
#define CPUID_EXT_DTES64 (1 << 2)
#define CPUID_EXT_MONITOR (1 << 3)
#define CPUID_EXT_DSCPL (1 << 4)
#define CPUID_EXT_VMX (1 << 5)
#define CPUID_EXT_SMX (1 << 6)
#define CPUID_EXT_EST (1 << 7)
#define CPUID_EXT_TM2 (1 << 8)
#define CPUID_EXT_SSSE3 (1 << 9)
#define CPUID_EXT_CID (1 << 10)
#define CPUID_EXT_FMA (1 << 12)
#define CPUID_EXT_CX16 (1 << 13)
#define CPUID_EXT_XTPR (1 << 14)
#define CPUID_EXT_PDCM (1 << 15)
#define CPUID_EXT_PCID (1 << 17)
#define CPUID_EXT_DCA (1 << 18)
#define CPUID_EXT_SSE41 (1 << 19)
#define CPUID_EXT_SSE42 (1 << 20)
#define CPUID_EXT_X2APIC (1 << 21)
#define CPUID_EXT_MOVBE (1 << 22)
#define CPUID_EXT_POPCNT (1 << 23)
#define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24)
#define CPUID_EXT_AES (1 << 25)
#define CPUID_EXT_XSAVE (1 << 26)
#define CPUID_EXT_OSXSAVE (1 << 27)
#define CPUID_EXT_AVX (1 << 28)
#define CPUID_EXT_F16C (1 << 29)
#define CPUID_EXT_RDRAND (1 << 30)
#define CPUID_EXT_HYPERVISOR (1 << 31)
#define CPUID_EXT_SSE3 (1U << 0)
#define CPUID_EXT_PCLMULQDQ (1U << 1)
#define CPUID_EXT_DTES64 (1U << 2)
#define CPUID_EXT_MONITOR (1U << 3)
#define CPUID_EXT_DSCPL (1U << 4)
#define CPUID_EXT_VMX (1U << 5)
#define CPUID_EXT_SMX (1U << 6)
#define CPUID_EXT_EST (1U << 7)
#define CPUID_EXT_TM2 (1U << 8)
#define CPUID_EXT_SSSE3 (1U << 9)
#define CPUID_EXT_CID (1U << 10)
#define CPUID_EXT_FMA (1U << 12)
#define CPUID_EXT_CX16 (1U << 13)
#define CPUID_EXT_XTPR (1U << 14)
#define CPUID_EXT_PDCM (1U << 15)
#define CPUID_EXT_PCID (1U << 17)
#define CPUID_EXT_DCA (1U << 18)
#define CPUID_EXT_SSE41 (1U << 19)
#define CPUID_EXT_SSE42 (1U << 20)
#define CPUID_EXT_X2APIC (1U << 21)
#define CPUID_EXT_MOVBE (1U << 22)
#define CPUID_EXT_POPCNT (1U << 23)
#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
#define CPUID_EXT_AES (1U << 25)
#define CPUID_EXT_XSAVE (1U << 26)
#define CPUID_EXT_OSXSAVE (1U << 27)
#define CPUID_EXT_AVX (1U << 28)
#define CPUID_EXT_F16C (1U << 29)
#define CPUID_EXT_RDRAND (1U << 30)
#define CPUID_EXT_HYPERVISOR (1U << 31)
#define CPUID_EXT2_FPU (1 << 0)
#define CPUID_EXT2_VME (1 << 1)
#define CPUID_EXT2_DE (1 << 2)
#define CPUID_EXT2_PSE (1 << 3)
#define CPUID_EXT2_TSC (1 << 4)
#define CPUID_EXT2_MSR (1 << 5)
#define CPUID_EXT2_PAE (1 << 6)
#define CPUID_EXT2_MCE (1 << 7)
#define CPUID_EXT2_CX8 (1 << 8)
#define CPUID_EXT2_APIC (1 << 9)
#define CPUID_EXT2_SYSCALL (1 << 11)
#define CPUID_EXT2_MTRR (1 << 12)
#define CPUID_EXT2_PGE (1 << 13)
#define CPUID_EXT2_MCA (1 << 14)
#define CPUID_EXT2_CMOV (1 << 15)
#define CPUID_EXT2_PAT (1 << 16)
#define CPUID_EXT2_PSE36 (1 << 17)
#define CPUID_EXT2_MP (1 << 19)
#define CPUID_EXT2_NX (1 << 20)
#define CPUID_EXT2_MMXEXT (1 << 22)
#define CPUID_EXT2_MMX (1 << 23)
#define CPUID_EXT2_FXSR (1 << 24)
#define CPUID_EXT2_FFXSR (1 << 25)
#define CPUID_EXT2_PDPE1GB (1 << 26)
#define CPUID_EXT2_RDTSCP (1 << 27)
#define CPUID_EXT2_LM (1 << 29)
#define CPUID_EXT2_3DNOWEXT (1 << 30)
#define CPUID_EXT2_3DNOW (1 << 31)
#define CPUID_EXT2_FPU (1U << 0)
#define CPUID_EXT2_VME (1U << 1)
#define CPUID_EXT2_DE (1U << 2)
#define CPUID_EXT2_PSE (1U << 3)
#define CPUID_EXT2_TSC (1U << 4)
#define CPUID_EXT2_MSR (1U << 5)
#define CPUID_EXT2_PAE (1U << 6)
#define CPUID_EXT2_MCE (1U << 7)
#define CPUID_EXT2_CX8 (1U << 8)
#define CPUID_EXT2_APIC (1U << 9)
#define CPUID_EXT2_SYSCALL (1U << 11)
#define CPUID_EXT2_MTRR (1U << 12)
#define CPUID_EXT2_PGE (1U << 13)
#define CPUID_EXT2_MCA (1U << 14)
#define CPUID_EXT2_CMOV (1U << 15)
#define CPUID_EXT2_PAT (1U << 16)
#define CPUID_EXT2_PSE36 (1U << 17)
#define CPUID_EXT2_MP (1U << 19)
#define CPUID_EXT2_NX (1U << 20)
#define CPUID_EXT2_MMXEXT (1U << 22)
#define CPUID_EXT2_MMX (1U << 23)
#define CPUID_EXT2_FXSR (1U << 24)
#define CPUID_EXT2_FFXSR (1U << 25)
#define CPUID_EXT2_PDPE1GB (1U << 26)
#define CPUID_EXT2_RDTSCP (1U << 27)
#define CPUID_EXT2_LM (1U << 29)
#define CPUID_EXT2_3DNOWEXT (1U << 30)
#define CPUID_EXT2_3DNOW (1U << 31)
/* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
@ -509,53 +509,53 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
#define CPUID_EXT3_LAHF_LM (1 << 0)
#define CPUID_EXT3_CMP_LEG (1 << 1)
#define CPUID_EXT3_SVM (1 << 2)
#define CPUID_EXT3_EXTAPIC (1 << 3)
#define CPUID_EXT3_CR8LEG (1 << 4)
#define CPUID_EXT3_ABM (1 << 5)
#define CPUID_EXT3_SSE4A (1 << 6)
#define CPUID_EXT3_MISALIGNSSE (1 << 7)
#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
#define CPUID_EXT3_OSVW (1 << 9)
#define CPUID_EXT3_IBS (1 << 10)
#define CPUID_EXT3_XOP (1 << 11)
#define CPUID_EXT3_SKINIT (1 << 12)
#define CPUID_EXT3_WDT (1 << 13)
#define CPUID_EXT3_LWP (1 << 15)
#define CPUID_EXT3_FMA4 (1 << 16)
#define CPUID_EXT3_TCE (1 << 17)
#define CPUID_EXT3_NODEID (1 << 19)
#define CPUID_EXT3_TBM (1 << 21)
#define CPUID_EXT3_TOPOEXT (1 << 22)
#define CPUID_EXT3_PERFCORE (1 << 23)
#define CPUID_EXT3_PERFNB (1 << 24)
#define CPUID_EXT3_LAHF_LM (1U << 0)
#define CPUID_EXT3_CMP_LEG (1U << 1)
#define CPUID_EXT3_SVM (1U << 2)
#define CPUID_EXT3_EXTAPIC (1U << 3)
#define CPUID_EXT3_CR8LEG (1U << 4)
#define CPUID_EXT3_ABM (1U << 5)
#define CPUID_EXT3_SSE4A (1U << 6)
#define CPUID_EXT3_MISALIGNSSE (1U << 7)
#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
#define CPUID_EXT3_OSVW (1U << 9)
#define CPUID_EXT3_IBS (1U << 10)
#define CPUID_EXT3_XOP (1U << 11)
#define CPUID_EXT3_SKINIT (1U << 12)
#define CPUID_EXT3_WDT (1U << 13)
#define CPUID_EXT3_LWP (1U << 15)
#define CPUID_EXT3_FMA4 (1U << 16)
#define CPUID_EXT3_TCE (1U << 17)
#define CPUID_EXT3_NODEID (1U << 19)
#define CPUID_EXT3_TBM (1U << 21)
#define CPUID_EXT3_TOPOEXT (1U << 22)
#define CPUID_EXT3_PERFCORE (1U << 23)
#define CPUID_EXT3_PERFNB (1U << 24)
#define CPUID_SVM_NPT (1 << 0)
#define CPUID_SVM_LBRV (1 << 1)
#define CPUID_SVM_SVMLOCK (1 << 2)
#define CPUID_SVM_NRIPSAVE (1 << 3)
#define CPUID_SVM_TSCSCALE (1 << 4)
#define CPUID_SVM_VMCBCLEAN (1 << 5)
#define CPUID_SVM_FLUSHASID (1 << 6)
#define CPUID_SVM_DECODEASSIST (1 << 7)
#define CPUID_SVM_PAUSEFILTER (1 << 10)
#define CPUID_SVM_PFTHRESHOLD (1 << 12)
#define CPUID_SVM_NPT (1U << 0)
#define CPUID_SVM_LBRV (1U << 1)
#define CPUID_SVM_SVMLOCK (1U << 2)
#define CPUID_SVM_NRIPSAVE (1U << 3)
#define CPUID_SVM_TSCSCALE (1U << 4)
#define CPUID_SVM_VMCBCLEAN (1U << 5)
#define CPUID_SVM_FLUSHASID (1U << 6)
#define CPUID_SVM_DECODEASSIST (1U << 7)
#define CPUID_SVM_PAUSEFILTER (1U << 10)
#define CPUID_SVM_PFTHRESHOLD (1U << 12)
#define CPUID_7_0_EBX_FSGSBASE (1 << 0)
#define CPUID_7_0_EBX_BMI1 (1 << 3)
#define CPUID_7_0_EBX_HLE (1 << 4)
#define CPUID_7_0_EBX_AVX2 (1 << 5)
#define CPUID_7_0_EBX_SMEP (1 << 7)
#define CPUID_7_0_EBX_BMI2 (1 << 8)
#define CPUID_7_0_EBX_ERMS (1 << 9)
#define CPUID_7_0_EBX_INVPCID (1 << 10)
#define CPUID_7_0_EBX_RTM (1 << 11)
#define CPUID_7_0_EBX_MPX (1 << 14)
#define CPUID_7_0_EBX_RDSEED (1 << 18)
#define CPUID_7_0_EBX_ADX (1 << 19)
#define CPUID_7_0_EBX_SMAP (1 << 20)
#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
#define CPUID_7_0_EBX_BMI1 (1U << 3)
#define CPUID_7_0_EBX_HLE (1U << 4)
#define CPUID_7_0_EBX_AVX2 (1U << 5)
#define CPUID_7_0_EBX_SMEP (1U << 7)
#define CPUID_7_0_EBX_BMI2 (1U << 8)
#define CPUID_7_0_EBX_ERMS (1U << 9)
#define CPUID_7_0_EBX_INVPCID (1U << 10)
#define CPUID_7_0_EBX_RTM (1U << 11)
#define CPUID_7_0_EBX_MPX (1U << 14)
#define CPUID_7_0_EBX_RDSEED (1U << 18)
#define CPUID_7_0_EBX_ADX (1U << 19)
#define CPUID_7_0_EBX_SMAP (1U << 20)
#define CPUID_VENDOR_SZ 12
@ -571,8 +571,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_VENDOR_VIA "CentaurHauls"
#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */
#define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */
#define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
#define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
#ifndef HYPERV_SPINLOCK_NEVER_RETRY
#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF

2
target-i386/kvm.c
View File

@ -122,7 +122,7 @@ static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
return cpuid;
}
struct kvm_para_features {
static const struct kvm_para_features {
int cap;
int feature;
} para_features[] = {

2
target-mips/cpu.h
View File

@ -775,7 +775,7 @@ static inline void compute_hflags(CPUMIPSState *env)
and disable the MIPS IV extensions to the MIPS III ISA.
Some other MIPS IV CPUs ignore the bit, so the check here
would be too restrictive for them. */
if (env->CP0_Status & (1 << CP0St_CU3)) {
if (env->CP0_Status & (1U << CP0St_CU3)) {
env->hflags |= MIPS_HFLAG_COP1X;
}
}

8
target-mips/helper.c
View File

@ -458,7 +458,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->hflags &= ~(MIPS_HFLAG_KSU);
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->CP0_Cause &= ~(1U << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00480;
set_hflags_for_handler(env);
break;
@ -478,7 +478,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->CP0_Cause &= ~(1U << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00000;
set_hflags_for_handler(env);
break;
@ -616,9 +616,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
env->CP0_EPC = exception_resume_pc(env);
if (env->hflags & MIPS_HFLAG_BMASK) {
env->CP0_Cause |= (1 << CP0Ca_BD);
env->CP0_Cause |= (1U << CP0Ca_BD);
} else {
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->CP0_Cause &= ~(1U << CP0Ca_BD);
}
env->CP0_Status |= (1 << CP0St_EXL);
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;

2
target-mips/op_helper.c
View File

@ -648,7 +648,7 @@ static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
{
uint32_t status;
uint32_t tcu, tmx, tasid, tksu;
uint32_t mask = ((1 << CP0St_CU3)
uint32_t mask = ((1U << CP0St_CU3)
| (1 << CP0St_CU2)
| (1 << CP0St_CU1)
| (1 << CP0St_CU0)

22
target-mips/translate_init.c
View File

@ -22,20 +22,20 @@
/* Have config1, uncached coherency */
#define MIPS_CONFIG0 \
((1 << CP0C0_M) | (0x2 << CP0C0_K0))
((1U << CP0C0_M) | (0x2 << CP0C0_K0))
/* Have config2, no coprocessor2 attached, no MDMX support attached,
no performance counters, watch registers present,
no code compression, EJTAG present, no FPU */
#define MIPS_CONFIG1 \
((1 << CP0C1_M) | \
((1U << CP0C1_M) | \
(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
(0 << CP0C1_FP))
/* Have config3, no tertiary/secondary caches implemented */
#define MIPS_CONFIG2 \
((1 << CP0C2_M))
((1U << CP0C2_M))
/* No config4, no DSP ASE, no large physaddr (PABITS),
no external interrupt controller, no vectored interrupts,
@ -301,16 +301,16 @@ static const mips_def_t mips_defs[] =
(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
.CP0_SRSConf0_rw_bitmask = 0x3fffffff,
.CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
.CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
(0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
.CP0_SRSConf1_rw_bitmask = 0x3fffffff,
.CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
.CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
(0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
.CP0_SRSConf2_rw_bitmask = 0x3fffffff,
.CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
.CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
(0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
.CP0_SRSConf3_rw_bitmask = 0x3fffffff,
.CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
.CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
(0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
.CP0_SRSConf4_rw_bitmask = 0x3fffffff,
.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
@ -355,8 +355,8 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
.CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
.CP0_Config4_rw_bitmask = 0,
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
.CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
@ -670,7 +670,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
programmable cache partitioning implemented, number of allocatable
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
implemented, 5 TCs implemented. */
env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
// TODO: actually do 2 VPEs.
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
@ -684,7 +684,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
(0x1 << CP0MVPC1_PCP1);
}

6
target-s390x/arch_dump.c
View File

@ -123,7 +123,7 @@ static void s390x_write_elf64_prefix(Note *note, S390CPU *cpu)
}
struct NoteFuncDescStruct {
static const struct NoteFuncDescStruct {
int contents_size;
void (*note_contents_func)(Note *note, S390CPU *cpu);
} note_func[] = {
@ -146,7 +146,7 @@ static int s390x_write_all_elf64_notes(const char *note_name,
void *opaque)
{
Note note;
NoteFuncDesc *nf;
const NoteFuncDesc *nf;
int note_size;
int ret = -1;
@ -192,7 +192,7 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
int name_size = 8; /* "CORE" or "QEMU" rounded */
size_t elf_note_size = 0;
int note_head_size;
NoteFuncDesc *nf;
const NoteFuncDesc *nf;
assert(class == ELFCLASS64);
assert(machine == EM_S390);

12
tests/libqos/pci-pc.c
View File

@ -110,37 +110,37 @@ static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value)
static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
return inb(0xcfc);
}
static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
return inw(0xcfc);
}
static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
return inl(0xcfc);
}
static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
outb(0xcfc, value);
}
static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
outw(0xcfc, value);
}
static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
outl(0xcfc, value);
}

2
util/module.c
View File

@ -163,7 +163,7 @@ out:
}
#endif
void module_load(module_init_type type)
static void module_load(module_init_type type)
{
#ifdef CONFIG_MODULES
char *fname = NULL;