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tcg/aarch64: Implement tlb lookup fast path
Supports CONFIG_QEMU_LDST_OPTIMIZATION Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
This commit is contained in:
Jani Kokkonen
Claudio Fontana
parent
b1f6dc0d2a
commit
c6d8ed24b4
2
configure
vendored
2
configure
vendored
@ -3594,7 +3594,7 @@ echo "libs_softmmu=$libs_softmmu" >> $config_host_mak
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echo "ARCH=$ARCH" >> $config_host_mak
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case "$cpu" in
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arm|i386|x86_64|ppc)
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arm|i386|x86_64|ppc|aarch64)
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# The TCG interpreter currently does not support ld/st optimization.
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if test "$tcg_interpreter" = "no" ; then
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echo "CONFIG_QEMU_LDST_OPTIMIZATION=y" >> $config_host_mak
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@ -358,6 +358,20 @@ static inline uintptr_t tcg_getpc_ldst(uintptr_t ra)
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not the start of the next opcode */
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return ra;
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}
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#elif defined(__aarch64__)
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# define GETRA() ((uintptr_t)__builtin_return_address(0))
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# define GETPC_LDST() tcg_getpc_ldst(GETRA())
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static inline uintptr_t tcg_getpc_ldst(uintptr_t ra)
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{
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int32_t b;
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ra += 4; /* skip one instruction */
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b = *(int32_t *)ra; /* load the branch insn */
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b = (b << 6) >> (6 - 2); /* extract the displacement */
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ra += b; /* apply the displacement */
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ra -= 4; /* return a pointer into the current opcode,
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not the start of the next opcode */
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return ra;
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}
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# else
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# error "CONFIG_QEMU_LDST_OPTIMIZATION needs GETPC_LDST() implementation!"
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# endif
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@ -732,6 +732,51 @@ static inline void tcg_out_uxt(TCGContext *s, int s_bits,
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tcg_out_ubfm(s, 0, rd, rn, 0, bits);
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}
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static inline void tcg_out_addi(TCGContext *s, int ext,
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TCGReg rd, TCGReg rn, unsigned int aimm)
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{
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/* add immediate aimm unsigned 12bit value (with LSL 0 or 12) */
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/* using ADD 0x11000000 | (ext) | (aimm << 10) | (rn << 5) | rd */
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unsigned int base = ext ? 0x91000000 : 0x11000000;
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if (aimm <= 0xfff) {
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aimm <<= 10;
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} else {
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/* we can only shift left by 12, on assert we cannot represent */
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assert(!(aimm & 0xfff));
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assert(aimm <= 0xfff000);
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base |= 1 << 22; /* apply LSL 12 */
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aimm >>= 2;
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}
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tcg_out32(s, base | aimm | (rn << 5) | rd);
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}
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static inline void tcg_out_subi(TCGContext *s, int ext,
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TCGReg rd, TCGReg rn, unsigned int aimm)
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{
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/* sub immediate aimm unsigned 12bit value (with LSL 0 or 12) */
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/* using SUB 0x51000000 | (ext) | (aimm << 10) | (rn << 5) | rd */
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unsigned int base = ext ? 0xd1000000 : 0x51000000;
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if (aimm <= 0xfff) {
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aimm <<= 10;
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} else {
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/* we can only shift left by 12, on assert we cannot represent */
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assert(!(aimm & 0xfff));
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assert(aimm <= 0xfff000);
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base |= 1 << 22; /* apply LSL 12 */
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aimm >>= 2;
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}
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tcg_out32(s, base | aimm | (rn << 5) | rd);
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}
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static inline void tcg_out_nop(TCGContext *s)
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{
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tcg_out32(s, 0xd503201f);
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}
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#ifdef CONFIG_SOFTMMU
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#include "exec/softmmu_defs.h"
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@ -753,7 +798,125 @@ static const void * const qemu_st_helpers[4] = {
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helper_stq_mmu,
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};
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#else /* !CONFIG_SOFTMMU */
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static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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reloc_pc19(lb->label_ptr[0], (tcg_target_long)s->code_ptr);
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tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0);
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tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index);
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
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(tcg_target_long)qemu_ld_helpers[lb->opc & 3]);
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tcg_out_callr(s, TCG_REG_TMP);
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if (lb->opc & 0x04) {
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tcg_out_sxt(s, 1, lb->opc & 3, lb->datalo_reg, TCG_REG_X0);
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} else {
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tcg_out_movr(s, 1, lb->datalo_reg, TCG_REG_X0);
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}
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tcg_out_goto(s, (tcg_target_long)lb->raddr);
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}
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static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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reloc_pc19(lb->label_ptr[0], (tcg_target_long)s->code_ptr);
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tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0);
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tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
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tcg_out_movr(s, 1, TCG_REG_X2, lb->datalo_reg);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
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(tcg_target_long)qemu_st_helpers[lb->opc & 3]);
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tcg_out_callr(s, TCG_REG_TMP);
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tcg_out_nop(s);
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tcg_out_goto(s, (tcg_target_long)lb->raddr);
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}
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void tcg_out_tb_finalize(TCGContext *s)
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{
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int i;
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for (i = 0; i < s->nb_qemu_ldst_labels; i++) {
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TCGLabelQemuLdst *label = &s->qemu_ldst_labels[i];
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if (label->is_ld) {
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tcg_out_qemu_ld_slow_path(s, label);
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} else {
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tcg_out_qemu_st_slow_path(s, label);
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}
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}
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}
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static void add_qemu_ldst_label(TCGContext *s, int is_ld, int opc,
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TCGReg data_reg, TCGReg addr_reg,
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int mem_index,
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uint8_t *raddr, uint8_t *label_ptr)
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{
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int idx;
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TCGLabelQemuLdst *label;
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if (s->nb_qemu_ldst_labels >= TCG_MAX_QEMU_LDST) {
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tcg_abort();
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}
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idx = s->nb_qemu_ldst_labels++;
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label = &s->qemu_ldst_labels[idx];
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label->is_ld = is_ld;
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label->opc = opc;
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label->datalo_reg = data_reg;
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label->addrlo_reg = addr_reg;
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label->mem_index = mem_index;
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label->raddr = raddr;
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label->label_ptr[0] = label_ptr;
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}
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/* Load and compare a TLB entry, emitting the conditional jump to the
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slow path for the failure case, which will be patched later when finalizing
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the slow path. Generated code returns the host addend in X1,
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clobbers X0,X2,X3,TMP. */
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static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
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int s_bits, uint8_t **label_ptr, int mem_index, int is_read)
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{
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TCGReg base = TCG_AREG0;
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int tlb_offset = is_read ?
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
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: offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
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/* Extract the TLB index from the address into X0.
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X0<CPU_TLB_BITS:0> =
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addr_reg<TARGET_PAGE_BITS+CPU_TLB_BITS:TARGET_PAGE_BITS> */
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tcg_out_ubfm(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, addr_reg,
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TARGET_PAGE_BITS, TARGET_PAGE_BITS + CPU_TLB_BITS);
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/* Store the page mask part of the address and the low s_bits into X3.
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Later this allows checking for equality and alignment at the same time.
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X3 = addr_reg & (PAGE_MASK | ((1 << s_bits) - 1)) */
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tcg_out_andi(s, (TARGET_LONG_BITS == 64), TCG_REG_X3, addr_reg,
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(TARGET_LONG_BITS - TARGET_PAGE_BITS) + s_bits,
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(TARGET_LONG_BITS - TARGET_PAGE_BITS));
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/* Add any "high bits" from the tlb offset to the env address into X2,
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to take advantage of the LSL12 form of the addi instruction.
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X2 = env + (tlb_offset & 0xfff000) */
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tcg_out_addi(s, 1, TCG_REG_X2, base, tlb_offset & 0xfff000);
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/* Merge the tlb index contribution into X2.
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X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */
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tcg_out_arith(s, ARITH_ADD, 1, TCG_REG_X2, TCG_REG_X2,
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TCG_REG_X0, -CPU_TLB_ENTRY_BITS);
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/* Merge "low bits" from tlb offset, load the tlb comparator into X0.
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X0 = load [X2 + (tlb_offset & 0x000fff)] */
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tcg_out_ldst(s, TARGET_LONG_BITS == 64 ? LDST_64 : LDST_32,
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LDST_LD, TCG_REG_X0, TCG_REG_X2,
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(tlb_offset & 0xfff));
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/* Load the tlb addend. Do that early to avoid stalling.
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X1 = load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */
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tcg_out_ldst(s, LDST_64, LDST_LD, TCG_REG_X1, TCG_REG_X2,
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(tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) -
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(is_read ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write)));
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/* Perform the address comparison. */
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tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0);
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*label_ptr = s->code_ptr;
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/* If not equal, we jump to the slow path. */
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tcg_out_goto_cond_noaddr(s, TCG_COND_NE);
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}
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#endif /* CONFIG_SOFTMMU */
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static void tcg_out_qemu_ld_direct(TCGContext *s, int opc, TCGReg data_r,
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TCGReg addr_r, TCGReg off_r)
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@ -841,13 +1004,13 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int opc, TCGReg data_r,
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tcg_abort();
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}
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}
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#endif /* CONFIG_SOFTMMU */
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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{
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TCGReg addr_reg, data_reg;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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uint8_t *label_ptr;
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#endif
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data_reg = args[0];
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addr_reg = args[1];
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@ -855,23 +1018,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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#ifdef CONFIG_SOFTMMU
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mem_index = args[2];
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s_bits = opc & 3;
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/* TODO: insert TLB lookup here */
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/* all arguments passed via registers */
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tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0);
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tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, addr_reg);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, mem_index);
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
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(tcg_target_long)qemu_ld_helpers[s_bits]);
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tcg_out_callr(s, TCG_REG_TMP);
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if (opc & 0x04) { /* sign extend */
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tcg_out_sxt(s, 1, s_bits, data_reg, TCG_REG_X0);
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} else {
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tcg_out_movr(s, 1, data_reg, TCG_REG_X0);
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}
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tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 1);
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tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, TCG_REG_X1);
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add_qemu_ldst_label(s, 1, opc, data_reg, addr_reg,
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mem_index, s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg,
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GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR);
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@ -883,6 +1033,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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TCGReg addr_reg, data_reg;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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uint8_t *label_ptr;
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#endif
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data_reg = args[0];
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addr_reg = args[1];
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@ -891,17 +1042,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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mem_index = args[2];
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s_bits = opc & 3;
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/* TODO: insert TLB lookup here */
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/* all arguments passed via registers */
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tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0);
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tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, addr_reg);
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tcg_out_movr(s, 1, TCG_REG_X2, data_reg);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, mem_index);
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
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(tcg_target_long)qemu_st_helpers[s_bits]);
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tcg_out_callr(s, TCG_REG_TMP);
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tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 0);
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tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, TCG_REG_X1);
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add_qemu_ldst_label(s, 0, opc, data_reg, addr_reg,
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mem_index, s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg,
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GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR);
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@ -1344,26 +1488,6 @@ static void tcg_target_init(TCGContext *s)
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tcg_add_target_add_op_defs(aarch64_op_defs);
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}
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static inline void tcg_out_addi(TCGContext *s, int ext,
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TCGReg rd, TCGReg rn, unsigned int aimm)
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{
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/* add immediate aimm unsigned 12bit value (we use LSL 0 - no shift) */
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/* using ADD 0x11000000 | (ext) | (aimm << 10) | (rn << 5) | rd */
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unsigned int base = ext ? 0x91000000 : 0x11000000;
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assert(aimm <= 0xfff);
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tcg_out32(s, base | (aimm << 10) | (rn << 5) | rd);
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}
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static inline void tcg_out_subi(TCGContext *s, int ext,
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TCGReg rd, TCGReg rn, unsigned int aimm)
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{
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/* sub immediate aimm unsigned 12bit value (we use LSL 0 - no shift) */
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/* using SUB 0x51000000 | (ext) | (aimm << 10) | (rn << 5) | rd */
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unsigned int base = ext ? 0xd1000000 : 0x51000000;
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assert(aimm <= 0xfff);
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tcg_out32(s, base | (aimm << 10) | (rn << 5) | rd);
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}
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static void tcg_target_qemu_prologue(TCGContext *s)
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{
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/* NB: frame sizes are in 16 byte stack units! */
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