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target/arm: Implement v8.1M REVIDR register
In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc and is a read-only IMPDEF register providing implementation specific minor revision information, like the v8A REVIDR_EL1. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-19-peter.maydell@linaro.org
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@ -1025,6 +1025,11 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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}
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return val;
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}
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case 0xcfc:
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if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) {
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goto bad_offset;
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}
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return cpu->revidr;
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case 0xd00: /* CPUID Base. */
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return cpu->midr;
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case 0xd04: /* Interrupt Control State (ICSR) */
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