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hardfloat: implement float32/64 fused multiply-add
Performance results for fp-bench: 1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz - before: fma-single: 74.73 MFlops fma-double: 74.54 MFlops - after: fma-single: 203.37 MFlops fma-double: 169.37 MFlops 2. ARM Aarch64 A57 @ 2.4GHz - before: fma-single: 23.24 MFlops fma-double: 23.70 MFlops - after: fma-single: 66.14 MFlops fma-double: 63.10 MFlops 3. IBM POWER8E @ 2.1 GHz - before: fma-single: 37.26 MFlops fma-double: 37.29 MFlops - after: fma-single: 48.90 MFlops fma-double: 59.51 MFlops Here having 3FP64 set to 1 pays off for x86_64: [1] 170.15 vs [0] 153.12 MFlops Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
This commit is contained in:
Emilio G. Cota
Alex Bennée
parent
4a6295613f
commit
ccf770ba73
132
fpu/softfloat.c
132
fpu/softfloat.c
@ -1518,8 +1518,9 @@ float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c,
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return float16_round_pack_canonical(pr, status);
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}
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float32 QEMU_FLATTEN float32_muladd(float32 a, float32 b, float32 c,
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int flags, float_status *status)
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static float32 QEMU_SOFTFLOAT_ATTR
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soft_f32_muladd(float32 a, float32 b, float32 c, int flags,
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float_status *status)
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{
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FloatParts pa = float32_unpack_canonical(a, status);
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FloatParts pb = float32_unpack_canonical(b, status);
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@ -1529,8 +1530,9 @@ float32 QEMU_FLATTEN float32_muladd(float32 a, float32 b, float32 c,
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return float32_round_pack_canonical(pr, status);
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}
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float64 QEMU_FLATTEN float64_muladd(float64 a, float64 b, float64 c,
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int flags, float_status *status)
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static float64 QEMU_SOFTFLOAT_ATTR
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soft_f64_muladd(float64 a, float64 b, float64 c, int flags,
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float_status *status)
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{
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FloatParts pa = float64_unpack_canonical(a, status);
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FloatParts pb = float64_unpack_canonical(b, status);
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@ -1540,6 +1542,128 @@ float64 QEMU_FLATTEN float64_muladd(float64 a, float64 b, float64 c,
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return float64_round_pack_canonical(pr, status);
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}
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float32 QEMU_FLATTEN
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float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status *s)
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{
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union_float32 ua, ub, uc, ur;
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ua.s = xa;
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ub.s = xb;
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uc.s = xc;
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if (unlikely(!can_use_fpu(s))) {
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goto soft;
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}
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if (unlikely(flags & float_muladd_halve_result)) {
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goto soft;
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}
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float32_input_flush3(&ua.s, &ub.s, &uc.s, s);
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if (unlikely(!f32_is_zon3(ua, ub, uc))) {
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goto soft;
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}
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/*
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* When (a || b) == 0, there's no need to check for under/over flow,
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* since we know the addend is (normal || 0) and the product is 0.
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*/
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if (float32_is_zero(ua.s) || float32_is_zero(ub.s)) {
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union_float32 up;
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bool prod_sign;
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prod_sign = float32_is_neg(ua.s) ^ float32_is_neg(ub.s);
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prod_sign ^= !!(flags & float_muladd_negate_product);
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up.s = float32_set_sign(float32_zero, prod_sign);
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if (flags & float_muladd_negate_c) {
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uc.h = -uc.h;
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}
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ur.h = up.h + uc.h;
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} else {
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if (flags & float_muladd_negate_product) {
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ua.h = -ua.h;
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}
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if (flags & float_muladd_negate_c) {
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uc.h = -uc.h;
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}
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ur.h = fmaf(ua.h, ub.h, uc.h);
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if (unlikely(f32_is_inf(ur))) {
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s->float_exception_flags |= float_flag_overflow;
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} else if (unlikely(fabsf(ur.h) <= FLT_MIN)) {
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goto soft;
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}
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}
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if (flags & float_muladd_negate_result) {
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return float32_chs(ur.s);
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}
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return ur.s;
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soft:
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return soft_f32_muladd(ua.s, ub.s, uc.s, flags, s);
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}
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float64 QEMU_FLATTEN
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float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s)
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{
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union_float64 ua, ub, uc, ur;
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ua.s = xa;
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ub.s = xb;
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uc.s = xc;
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if (unlikely(!can_use_fpu(s))) {
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goto soft;
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}
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if (unlikely(flags & float_muladd_halve_result)) {
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goto soft;
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}
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float64_input_flush3(&ua.s, &ub.s, &uc.s, s);
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if (unlikely(!f64_is_zon3(ua, ub, uc))) {
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goto soft;
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}
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/*
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* When (a || b) == 0, there's no need to check for under/over flow,
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* since we know the addend is (normal || 0) and the product is 0.
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*/
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if (float64_is_zero(ua.s) || float64_is_zero(ub.s)) {
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union_float64 up;
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bool prod_sign;
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prod_sign = float64_is_neg(ua.s) ^ float64_is_neg(ub.s);
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prod_sign ^= !!(flags & float_muladd_negate_product);
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up.s = float64_set_sign(float64_zero, prod_sign);
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if (flags & float_muladd_negate_c) {
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uc.h = -uc.h;
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}
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ur.h = up.h + uc.h;
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} else {
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if (flags & float_muladd_negate_product) {
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ua.h = -ua.h;
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}
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if (flags & float_muladd_negate_c) {
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uc.h = -uc.h;
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}
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ur.h = fma(ua.h, ub.h, uc.h);
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if (unlikely(f64_is_inf(ur))) {
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s->float_exception_flags |= float_flag_overflow;
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} else if (unlikely(fabs(ur.h) <= FLT_MIN)) {
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goto soft;
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}
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}
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if (flags & float_muladd_negate_result) {
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return float64_chs(ur.s);
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}
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return ur.s;
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soft:
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return soft_f64_muladd(ua.s, ub.s, uc.s, flags, s);
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}
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/*
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* Returns the result of dividing the floating-point value `a' by the
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* corresponding value `b'. The operation is performed according to
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