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target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user

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This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
(indirect branch from register other than x16/x17).  The linux kernel
sets this in bti_enable().

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220427042312.294300-1-richard.henderson@linaro.org
[PMM: remove stray change to makefile comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-26 21:23:12 -07:00 committed by Peter Maydell
parent 1fba9dc71a
commit cda86e2b46
3 changed files with 47 additions and 3 deletions
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2
target/arm/cpu.c
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@ -197,6 +197,8 @@ static void arm_cpu_reset(DeviceState *dev)
/* Enable all PAC keys. */
env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
SCTLR_EnDA | SCTLR_EnDB);
/* Trap on btype=3 for PACIxSP. */
env->cp15.sctlr_el[1] |= SCTLR_BT0;
/* and to the FP/Neon instructions */
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
/* and to the SVE instructions */

6
tests/tcg/aarch64/Makefile.target
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@ -28,9 +28,9 @@ endif
# BTI Tests
# bti-1 tests the elf notes, so we require special compiler support.
ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
AARCH64_TESTS += bti-1
bti-1: CFLAGS += -mbranch-protection=standard
bti-1: LDFLAGS += -nostdlib
AARCH64_TESTS += bti-1 bti-3
bti-1 bti-3: CFLAGS += -mbranch-protection=standard
bti-1 bti-3: LDFLAGS += -nostdlib
endif
# bti-2 tests PROT_BTI, so no special compiler support required.
AARCH64_TESTS += bti-2

42
tests/tcg/aarch64/bti-3.c Normal file
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@ -0,0 +1,42 @@
/*
* BTI vs PACIASP
*/
#include "bti-crt.inc.c"
static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
{
uc->uc_mcontext.pc += 8;
uc->uc_mcontext.pstate = 1;
}
#define BTYPE_1() \
asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
: "=r"(skipped) : : "x16", "x30")
#define BTYPE_2() \
asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
: "=r"(skipped) : : "x16", "x30")
#define BTYPE_3() \
asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
: "=r"(skipped) : : "x15", "x30")
#define TEST(WHICH, EXPECT) \
do { WHICH(); fail += skipped ^ EXPECT; } while (0)
int main()
{
int fail = 0;
int skipped;
/* Signal-like with SA_SIGINFO. */
signal_info(SIGILL, skip2_sigill);
/* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */
TEST(BTYPE_1, 0);
TEST(BTYPE_2, 0);
TEST(BTYPE_3, 1);
return fail;
}