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tcg-arm: Split out tcg_out_tlb_read
Share code between qemu_ld and qemu_st to process the tlb. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
Aurelien Jarno
parent
9feac1d770
commit
cee87be80a
@ -1147,40 +1147,15 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
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argreg = tcg_out_arg_reg32(s, argreg, arghi);
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return argreg;
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}
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#endif /* SOFTMMU */
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#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
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static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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/* Load and compare a TLB entry, leaving the flags set. Leaves R0 pointing
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to the tlb entry. Clobbers R1 and TMP. */
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static void tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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int s_bits, int tlb_offset)
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{
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int addr_reg, data_reg, data_reg2, bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits, tlb_offset;
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TCGReg argreg;
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# if TARGET_LONG_BITS == 64
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int addr_reg2;
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# endif
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uint32_t *label_ptr;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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data_reg = *args++;
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if (opc == 3)
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data_reg2 = *args++;
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else
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data_reg2 = 0; /* suppress warning */
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addr_reg = *args++;
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#ifdef CONFIG_SOFTMMU
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# if TARGET_LONG_BITS == 64
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addr_reg2 = *args++;
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# endif
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mem_index = *args;
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s_bits = opc & 3;
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/* Should generate something like the following:
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* shr r8, addr_reg, #TARGET_PAGE_BITS
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* and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
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@ -1190,13 +1165,13 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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# error
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# endif
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP,
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0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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tcg_out_dat_imm(s, COND_AL, ARITH_AND,
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TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1);
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
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TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
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/* We assume that the offset is contained within 20 bits. */
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tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
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assert((tlb_offset & ~0xfffff) == 0);
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if (tlb_offset > 0xfff) {
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
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@ -1206,16 +1181,48 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
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TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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/* Check alignment. */
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if (s_bits)
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if (s_bits) {
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tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
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0, addr_reg, (1 << s_bits) - 1);
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# if TARGET_LONG_BITS == 64
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/* XXX: possibly we could use a block data load in the first access. */
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4);
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
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TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
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# endif
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0, addrlo, (1 << s_bits) - 1);
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}
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if (TARGET_LONG_BITS == 64) {
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/* XXX: possibly we could use a block data load in the first access. */
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4);
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
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TCG_REG_R1, addrhi, SHIFT_IMM_LSL(0));
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}
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}
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#endif /* SOFTMMU */
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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{
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TCGReg addr_reg, data_reg, data_reg2;
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bool bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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TCGReg argreg, addr_reg2;
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uint32_t *label_ptr;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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data_reg = *args++;
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data_reg2 = (opc == 3 ? *args++ : 0);
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addr_reg = *args++;
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#ifdef CONFIG_SOFTMMU
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addr_reg2 = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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mem_index = *args;
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s_bits = opc & 3;
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tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_read));
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_read));
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@ -1271,11 +1278,11 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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*/
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argreg = TCG_REG_R0;
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argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
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#if TARGET_LONG_BITS == 64
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argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
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#else
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argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
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#endif
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if (TARGET_LONG_BITS == 64) {
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argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
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} else {
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argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
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}
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argreg = tcg_out_arg_imm32(s, argreg, mem_index);
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tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[s_bits]);
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@ -1302,8 +1309,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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#else /* !CONFIG_SOFTMMU */
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if (GUEST_BASE) {
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uint32_t offset = GUEST_BASE;
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int i;
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int rot;
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int i, rot;
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while (offset) {
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i = ctz32(offset) & ~1;
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@ -1362,68 +1368,33 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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#endif
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}
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static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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{
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int addr_reg, data_reg, data_reg2, bswap;
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TCGReg addr_reg, data_reg, data_reg2;
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bool bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits, tlb_offset;
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TCGReg argreg;
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# if TARGET_LONG_BITS == 64
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int addr_reg2;
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# endif
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int mem_index, s_bits;
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TCGReg argreg, addr_reg2;
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uint32_t *label_ptr;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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data_reg = *args++;
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if (opc == 3)
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data_reg2 = *args++;
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else
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data_reg2 = 0; /* suppress warning */
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data_reg2 = (opc == 3 ? *args++ : 0);
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addr_reg = *args++;
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#ifdef CONFIG_SOFTMMU
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# if TARGET_LONG_BITS == 64
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addr_reg2 = *args++;
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# endif
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addr_reg2 = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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mem_index = *args;
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s_bits = opc & 3;
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/* Should generate something like the following:
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* shr r8, addr_reg, #TARGET_PAGE_BITS
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* and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
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* add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
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*/
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
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TCG_REG_TMP, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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tcg_out_dat_imm(s, COND_AL, ARITH_AND,
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TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1);
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
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TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
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/* We assume that the offset is contained within 20 bits. */
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tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
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assert((tlb_offset & ~0xfffff) == 0);
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if (tlb_offset > 0xfff) {
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
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0xa00 | (tlb_offset >> 12));
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tlb_offset &= 0xfff;
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}
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tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
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TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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/* Check alignment. */
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if (s_bits)
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tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
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0, addr_reg, (1 << s_bits) - 1);
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# if TARGET_LONG_BITS == 64
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/* XXX: possibly we could use a block data load in the first access. */
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4);
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
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TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
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# endif
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tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits,
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offsetof(CPUArchState,
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tlb_table[mem_index][0].addr_write));
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_write));
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@ -1472,11 +1443,11 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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*/
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argreg = TCG_REG_R0;
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argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
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#if TARGET_LONG_BITS == 64
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argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
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#else
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argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
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#endif
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if (TARGET_LONG_BITS == 64) {
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argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
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} else {
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argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
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}
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switch (opc) {
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case 0:
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