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target-ppc: convert load/store with reservation instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5830 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
bdb4b68907
commit
cf360a32af
@ -20,232 +20,6 @@
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#include "op_mem_access.h"
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/* Load and set reservation */
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void OPPROTO glue(op_lwarx, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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T1 = glue(ldu32, MEMSUFFIX)((uint32_t)T0);
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env->reserve = (uint32_t)T0;
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}
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RETURN();
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}
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#if defined(TARGET_PPC64)
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void OPPROTO glue(op_lwarx_64, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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T1 = glue(ldu32, MEMSUFFIX)((uint64_t)T0);
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env->reserve = (uint64_t)T0;
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}
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RETURN();
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}
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void OPPROTO glue(op_ldarx, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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T1 = glue(ldu64, MEMSUFFIX)((uint32_t)T0);
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env->reserve = (uint32_t)T0;
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}
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RETURN();
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}
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void OPPROTO glue(op_ldarx_64, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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T1 = glue(ldu64, MEMSUFFIX)((uint64_t)T0);
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env->reserve = (uint64_t)T0;
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}
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RETURN();
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}
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#endif
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void OPPROTO glue(op_lwarx_le, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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T1 = glue(ldu32r, MEMSUFFIX)((uint32_t)T0);
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env->reserve = (uint32_t)T0;
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}
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RETURN();
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}
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#if defined(TARGET_PPC64)
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void OPPROTO glue(op_lwarx_le_64, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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T1 = glue(ldu32r, MEMSUFFIX)((uint64_t)T0);
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env->reserve = (uint64_t)T0;
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}
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RETURN();
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}
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void OPPROTO glue(op_ldarx_le, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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T1 = glue(ldu64r, MEMSUFFIX)((uint32_t)T0);
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env->reserve = (uint32_t)T0;
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}
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RETURN();
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}
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void OPPROTO glue(op_ldarx_le_64, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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T1 = glue(ldu64r, MEMSUFFIX)((uint64_t)T0);
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env->reserve = (uint64_t)T0;
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}
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RETURN();
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}
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#endif
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/* Store with reservation */
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void OPPROTO glue(op_stwcx, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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if (unlikely(env->reserve != (uint32_t)T0)) {
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env->crf[0] = xer_so;
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} else {
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glue(st32, MEMSUFFIX)((uint32_t)T0, T1);
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env->crf[0] = xer_so | 0x02;
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}
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}
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env->reserve = (target_ulong)-1ULL;
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RETURN();
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}
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#if defined(TARGET_PPC64)
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void OPPROTO glue(op_stwcx_64, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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if (unlikely(env->reserve != (uint64_t)T0)) {
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env->crf[0] = xer_so;
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} else {
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glue(st32, MEMSUFFIX)((uint64_t)T0, T1);
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env->crf[0] = xer_so | 0x02;
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}
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}
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env->reserve = (target_ulong)-1ULL;
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RETURN();
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}
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void OPPROTO glue(op_stdcx, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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if (unlikely(env->reserve != (uint32_t)T0)) {
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env->crf[0] = xer_so;
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} else {
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glue(st64, MEMSUFFIX)((uint32_t)T0, T1);
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env->crf[0] = xer_so | 0x02;
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}
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}
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env->reserve = (target_ulong)-1ULL;
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RETURN();
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}
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void OPPROTO glue(op_stdcx_64, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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if (unlikely(env->reserve != (uint64_t)T0)) {
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env->crf[0] = xer_so;
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} else {
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glue(st64, MEMSUFFIX)((uint64_t)T0, T1);
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env->crf[0] = xer_so | 0x02;
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}
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}
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env->reserve = (target_ulong)-1ULL;
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RETURN();
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}
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#endif
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void OPPROTO glue(op_stwcx_le, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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if (unlikely(env->reserve != (uint32_t)T0)) {
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env->crf[0] = xer_so;
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} else {
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glue(st32r, MEMSUFFIX)((uint32_t)T0, T1);
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env->crf[0] = xer_so | 0x02;
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}
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}
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env->reserve = (target_ulong)-1ULL;
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RETURN();
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}
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#if defined(TARGET_PPC64)
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void OPPROTO glue(op_stwcx_le_64, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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if (unlikely(env->reserve != (uint64_t)T0)) {
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env->crf[0] = xer_so;
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} else {
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glue(st32r, MEMSUFFIX)((uint64_t)T0, T1);
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env->crf[0] = xer_so | 0x02;
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}
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}
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env->reserve = (target_ulong)-1ULL;
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RETURN();
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}
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void OPPROTO glue(op_stdcx_le, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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if (unlikely(env->reserve != (uint32_t)T0)) {
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env->crf[0] = xer_so;
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} else {
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glue(st64r, MEMSUFFIX)((uint32_t)T0, T1);
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env->crf[0] = xer_so | 0x02;
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}
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}
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env->reserve = (target_ulong)-1ULL;
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RETURN();
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}
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void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void)
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{
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if (unlikely(T0 & 0x03)) {
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raise_exception(env, POWERPC_EXCP_ALIGN);
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} else {
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if (unlikely(env->reserve != (uint64_t)T0)) {
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env->crf[0] = xer_so;
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} else {
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glue(st64r, MEMSUFFIX)((uint64_t)T0, T1);
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env->crf[0] = xer_so | 0x02;
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}
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}
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env->reserve = (target_ulong)-1ULL;
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RETURN();
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}
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#endif
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/* External access */
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void OPPROTO glue(op_eciwx, MEMSUFFIX) (void)
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{
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@ -66,6 +66,7 @@ static TCGv cpu_nip;
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static TCGv cpu_ctr;
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static TCGv cpu_lr;
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static TCGv cpu_xer;
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static TCGv cpu_reserve;
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static TCGv_i32 cpu_fpscr;
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static TCGv_i32 cpu_access_type;
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@ -161,6 +162,9 @@ void ppc_translate_init(void)
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cpu_xer = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, xer), "xer");
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cpu_reserve = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, reserve), "reserve");
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cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, fpscr), "fpscr");
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@ -2468,6 +2472,24 @@ static always_inline void gen_addr_register (TCGv EA,
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tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
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}
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static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
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{
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int l1 = gen_new_label();
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TCGv t0 = tcg_temp_new();
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TCGv_i32 t1, t2;
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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tcg_gen_andi_tl(t0, EA, mask);
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tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
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t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
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t2 = tcg_const_i32(0);
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gen_helper_raise_exception_err(t1, t2);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t2);
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gen_set_label(l1);
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tcg_temp_free(t0);
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}
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#if defined(TARGET_PPC64)
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#define _GEN_MEM_FUNCS(name, mode) \
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&gen_op_##name##_##mode, \
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@ -3220,67 +3242,79 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
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GEN_STOP(ctx);
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}
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#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
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#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
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static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
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GEN_MEM_FUNCS(lwarx),
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};
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static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
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GEN_MEM_FUNCS(stwcx),
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};
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/* lwarx */
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GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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TCGv t0 = tcg_temp_local_new();
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gen_set_access_type(ACCESS_RES);
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gen_addr_reg_index(cpu_T[0], ctx);
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op_lwarx();
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tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
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gen_addr_reg_index(t0, ctx);
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gen_check_align(ctx, t0, 0x03);
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#if defined(TARGET_PPC64)
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if (!ctx->sf_mode)
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tcg_gen_ext32u_tl(t0, t0);
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#endif
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gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
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tcg_gen_mov_tl(cpu_reserve, t0);
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tcg_temp_free(t0);
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}
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/* stwcx. */
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GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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int l1 = gen_new_label();
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TCGv t0 = tcg_temp_local_new();
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gen_set_access_type(ACCESS_RES);
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gen_addr_reg_index(cpu_T[0], ctx);
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tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
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op_stwcx();
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gen_addr_reg_index(t0, ctx);
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gen_check_align(ctx, t0, 0x03);
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#if defined(TARGET_PPC64)
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if (!ctx->sf_mode)
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tcg_gen_ext32u_tl(t0, t0);
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#endif
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tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
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tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
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tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
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tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
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tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
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gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
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gen_set_label(l1);
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tcg_gen_movi_tl(cpu_reserve, -1);
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tcg_temp_free(t0);
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}
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#if defined(TARGET_PPC64)
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#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
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#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
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static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
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GEN_MEM_FUNCS(ldarx),
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};
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static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
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GEN_MEM_FUNCS(stdcx),
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};
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/* ldarx */
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GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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TCGv t0 = tcg_temp_local_new();
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gen_set_access_type(ACCESS_RES);
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gen_addr_reg_index(cpu_T[0], ctx);
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op_ldarx();
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tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
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gen_addr_reg_index(t0, ctx);
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gen_check_align(ctx, t0, 0x07);
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if (!ctx->sf_mode)
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tcg_gen_ext32u_tl(t0, t0);
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gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
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tcg_gen_mov_tl(cpu_reserve, t0);
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tcg_temp_free(t0);
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}
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/* stdcx. */
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GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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int l1 = gen_new_label();
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TCGv t0 = tcg_temp_local_new();
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gen_set_access_type(ACCESS_RES);
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gen_addr_reg_index(cpu_T[0], ctx);
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tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
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op_stdcx();
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gen_addr_reg_index(t0, ctx);
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gen_check_align(ctx, t0, 0x07);
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if (!ctx->sf_mode)
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
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tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
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tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
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tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
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tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
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gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
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gen_set_label(l1);
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tcg_gen_movi_tl(cpu_reserve, -1);
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tcg_temp_free(t0);
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}
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#endif /* defined(TARGET_PPC64) */
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