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esp: latch individual bits in ESP_RINTR register
Currently the ESP_RINTR register is set to a specific value as required within the ESP state machine. In order to implement the upcoming deferred interrupt functionality it is necessary to set individual bits within ESP_RINTR so that a deferred interrupt will not overwrite the value of any other interrupt bits. This also requires fixing up a few locations where the ESP_RINTR and ESP_RSEQ registers are set/reset unexpectedly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-33-mark.cave-ayland@ilande.co.uk>
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@ -178,7 +178,7 @@ static int esp_select(ESPState *s)
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if (!s->current_dev) {
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/* No such drive */
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s->rregs[ESP_RSTAT] = 0;
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s->rregs[ESP_RINTR] = INTR_DC;
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s->rregs[ESP_RINTR] |= INTR_DC;
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s->rregs[ESP_RSEQ] = SEQ_0;
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esp_raise_irq(s);
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return -1;
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@ -245,7 +245,7 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
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}
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scsi_req_continue(s->current_req);
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}
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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esp_lower_drq(s);
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@ -326,7 +326,7 @@ static void satn_stop_pdma_cb(ESPState *s)
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trace_esp_handle_satn_stop(s->cmdlen);
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s->do_cmd = 1;
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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}
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@ -346,8 +346,8 @@ static void handle_satn_stop(ESPState *s)
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trace_esp_handle_satn_stop(s->cmdlen);
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s->cmdlen = cmdlen;
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s->do_cmd = 1;
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSTAT] = STAT_CD;
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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} else if (cmdlen == 0) {
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@ -362,7 +362,7 @@ static void handle_satn_stop(ESPState *s)
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static void write_response_pdma_cb(ESPState *s)
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{
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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}
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@ -376,7 +376,7 @@ static void write_response(ESPState *s)
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if (s->dma_memory_write) {
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s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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} else {
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s->pdma_cb = write_response_pdma_cb;
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@ -395,7 +395,7 @@ static void write_response(ESPState *s)
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static void esp_dma_done(ESPState *s)
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{
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s->rregs[ESP_RSTAT] |= STAT_TC;
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s->rregs[ESP_RINTR] = INTR_BS;
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s->rregs[ESP_RINTR] |= INTR_BS;
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s->rregs[ESP_RSEQ] = 0;
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s->rregs[ESP_RFLAGS] = 0;
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esp_set_tc(s, 0);
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@ -700,7 +700,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
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val = s->rregs[ESP_RINTR];
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s->rregs[ESP_RINTR] = 0;
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s->rregs[ESP_RSTAT] &= ~STAT_TC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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s->rregs[ESP_RSEQ] = SEQ_0;
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esp_lower_irq(s);
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if (s->deferred_complete) {
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esp_report_command_complete(s, s->deferred_status);
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@ -771,9 +771,6 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
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/*s->ti_size = 0;*/
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s->ti_wptr = 0;
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s->ti_rptr = 0;
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s->rregs[ESP_RINTR] = INTR_FC;
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s->rregs[ESP_RSEQ] = 0;
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s->rregs[ESP_RFLAGS] = 0;
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break;
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case CMD_RESET:
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trace_esp_mem_writeb_cmd_reset(val);
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@ -781,8 +778,8 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
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break;
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case CMD_BUSRESET:
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trace_esp_mem_writeb_cmd_bus_reset(val);
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s->rregs[ESP_RINTR] = INTR_RST;
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if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
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s->rregs[ESP_RINTR] |= INTR_RST;
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esp_raise_irq(s);
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}
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break;
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@ -793,12 +790,12 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
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case CMD_ICCS:
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trace_esp_mem_writeb_cmd_iccs(val);
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write_response(s);
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s->rregs[ESP_RINTR] = INTR_FC;
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s->rregs[ESP_RINTR] |= INTR_FC;
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s->rregs[ESP_RSTAT] |= STAT_MI;
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break;
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case CMD_MSGACC:
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trace_esp_mem_writeb_cmd_msgacc(val);
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s->rregs[ESP_RINTR] = INTR_DC;
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s->rregs[ESP_RINTR] |= INTR_DC;
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s->rregs[ESP_RSEQ] = 0;
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s->rregs[ESP_RFLAGS] = 0;
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esp_raise_irq(s);
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@ -806,7 +803,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
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case CMD_PAD:
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trace_esp_mem_writeb_cmd_pad(val);
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s->rregs[ESP_RSTAT] = STAT_TC;
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s->rregs[ESP_RINTR] = INTR_FC;
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s->rregs[ESP_RINTR] |= INTR_FC;
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s->rregs[ESP_RSEQ] = 0;
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break;
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case CMD_SATN:
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