xemu-project/xemu
1
0
Fork 0
mirror of https://github.com/xemu-project/xemu.git synced 2024-11-23 19:49:43 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Clean out the N32 macros from target-mips, and introduce MIPS ABI specific

Browse Source 
defines for linux-user.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3556 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-11-08 18:05:37 +00:00
parent 5850586c07
commit d26bc2118e
13 changed files with 75 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
configure vendored
View File

@ -1099,16 +1099,18 @@ elif test "$target_cpu" = "mips" -o "$target_cpu" = "mipsel" ; then
echo "TARGET_ARCH=mips" >> $config_mak
echo "#define TARGET_ARCH \"mips\"" >> $config_h
echo "#define TARGET_MIPS 1" >> $config_h
echo "#define TARGET_ABI_MIPSO32 1" >> $config_h
elif test "$target_cpu" = "mipsn32" -o "$target_cpu" = "mipsn32el" ; then
echo "TARGET_ARCH=mipsn32" >> $config_mak
echo "#define TARGET_ARCH \"mipsn32\"" >> $config_h
echo "#define TARGET_MIPS 1" >> $config_h
echo "#define TARGET_MIPSN32 1" >> $config_h
echo "#define TARGET_ABI_MIPSN32 1" >> $config_h
elif test "$target_cpu" = "mips64" -o "$target_cpu" = "mips64el" ; then
echo "TARGET_ARCH=mips64" >> $config_mak
echo "#define TARGET_ARCH \"mips64\"" >> $config_h
echo "#define TARGET_MIPS 1" >> $config_h
echo "#define TARGET_MIPS64 1" >> $config_h
echo "#define TARGET_ABI_MIPSN64 1" >> $config_h
elif test "$target_cpu" = "cris" ; then
echo "TARGET_ARCH=cris" >> $config_mak
echo "#define TARGET_ARCH \"cris\"" >> $config_h

2
linux-user/main.c
View File

@ -2225,7 +2225,7 @@ int main(int argc, char **argv)
/* Choose and initialise CPU */
if (cpu_model == NULL)
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
cpu_model = "20Kc";
#else
cpu_model = "24Kf";

6
linux-user/signal.c
View File

@ -1939,7 +1939,7 @@ void sparc64_get_context(CPUSPARCState *env)
force_sig(SIGSEGV);
}
#endif
#elif defined(TARGET_MIPS64)
#elif defined(TARGET_ABI_MIPSN64)
# warning signal handling not implemented
@ -1968,7 +1968,7 @@ long do_rt_sigreturn(CPUState *env)
return -ENOSYS;
}
#elif defined(TARGET_MIPSN32)
#elif defined(TARGET_ABI_MIPSN32)
# warning signal handling not implemented
@ -1997,7 +1997,7 @@ long do_rt_sigreturn(CPUState *env)
return -ENOSYS;
}
#elif defined(TARGET_MIPS)
#elif defined(TARGET_ABI_MIPSO32)
struct target_sigcontext {
uint32_t sc_regmask; /* Unused */

14
linux-user/syscall_defs.h
View File

@ -307,8 +307,8 @@ int do_sigaction(int sig, const struct target_sigaction *act,
#define TARGET_SA_NODEFER 0x40000000
#define TARGET_SA_RESTART 0x10000000
#define TARGET_SA_RESETHAND 0x80000000
#if !defined(TARGET_MIPSN32) && !defined(TARGET_MIPS64)
#define TARGET_SA_RESTORER 0x04000000 /* Only for o32 */
#if !defined(TARGET_ABI_MIPSN32) && !defined(TARGET_ABI_MIPSN64)
#define TARGET_SA_RESTORER 0x04000000 /* Only for O32 */
#endif
#else
#define TARGET_SA_NOCLDSTOP 0x00000001
@ -450,7 +450,7 @@ int do_sigaction(int sig, const struct target_sigaction *act,
struct target_sigaction {
uint32_t sa_flags;
#if defined(TARGET_MIPSN32)
#if defined(TARGET_ABI_MIPSN32)
uint32_t _sa_handler;
#else
abi_ulong _sa_handler;
@ -1194,7 +1194,7 @@ struct target_stat64 {
unsigned long long st_ino;
} __attribute__((packed));
#elif defined(TARGET_MIPS64)
#elif defined(TARGET_ABI_MIPSN64)
/* The memory layout is the same as of struct stat64 of the 32-bit kernel. */
struct target_stat {
@ -1233,7 +1233,7 @@ struct target_stat {
abi_ulong st_blocks;
};
#elif defined(TARGET_MIPSN32)
#elif defined(TARGET_ABI_MIPSN32)
struct target_stat {
unsigned st_dev;
@ -1304,7 +1304,7 @@ struct target_stat64 {
int st_blocks;
};
#elif defined(TARGET_MIPS)
#elif defined(TARGET_ABI_MIPSO32)
struct target_stat {
unsigned st_dev;
@ -1486,7 +1486,7 @@ typedef struct {
} target_fsid_t;
#ifdef TARGET_MIPS
#ifdef TARGET_MIPSN32
#ifdef TARGET_ABI_MIPSN32
struct target_statfs {
int32_t f_type;
int32_t f_bsize;

6
target-mips/exec.h
View File

@ -56,7 +56,7 @@ register target_ulong T2 asm(AREG3);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_dsll (void);
void do_dsll32 (void);
@ -86,7 +86,7 @@ void do_maddu (void);
void do_msub (void);
void do_msubu (void);
#endif
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
void do_ddiv (void);
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_ddivu (void);
@ -236,7 +236,7 @@ static always_inline void compute_hflags(CPUState *env)
!(env->hflags & MIPS_HFLAG_DM)) {
env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
(env->CP0_Status & (1 << CP0St_PX)) ||
(env->CP0_Status & (1 << CP0St_UX)))

16
target-mips/helper.c
View File

@ -76,7 +76,7 @@ int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
target_ulong tag = address & ~mask;
target_ulong VPN = tlb->VPN & ~mask;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
tag &= env->SEGMask;
#endif
@ -108,7 +108,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
int kernel_mode = !user_mode && !supervisor_mode;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
@ -130,7 +130,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
} else {
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
} else if (address < 0x4000000000000000ULL) {
/* xuseg */
if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
@ -305,7 +305,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
((address >> 9) & 0x007ffff0);
env->CP0_EntryHi =
(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
env->CP0_EntryHi &= env->SEGMask;
env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
@ -425,7 +425,7 @@ void do_interrupt (CPUState *env)
case EXCP_TLBL:
cause = 2;
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
int R = env->CP0_BadVAddr >> 62;
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
@ -473,7 +473,7 @@ void do_interrupt (CPUState *env)
case EXCP_TLBS:
cause = 3;
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
int R = env->CP0_BadVAddr >> 62;
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
@ -559,7 +559,7 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
if (tlb->V0) {
addr = tlb->VPN & ~mask;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
addr |= 0x3FFFFF0000000000ULL;
}
@ -572,7 +572,7 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
}
if (tlb->V1) {
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
addr |= 0x3FFFFF0000000000ULL;
}

2
target-mips/mips-defs.h
View File

@ -8,7 +8,7 @@
#define TARGET_PAGE_BITS 12
#define MIPS_TLB_MAX 128
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
#define TARGET_LONG_BITS 64
#else
#define TARGET_LONG_BITS 32

24
target-mips/op.c
View File

@ -301,7 +301,7 @@ void op_addr_add (void)
/* For compatibility with 32-bit code, data reference in user mode
with Status_UX = 0 should be casted to 32-bit and sign extended.
See the MIPS64 PRA manual, section 4.10. */
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(env->CP0_Status & (1 << CP0St_UX)))
T0 = (int64_t)(int32_t)(T0 + T1);
@ -384,7 +384,7 @@ void op_divu (void)
RETURN();
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
/* Arithmetic */
void op_dadd (void)
{
@ -453,7 +453,7 @@ void op_ddivu (void)
RETURN();
}
#endif
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
#endif /* TARGET_MIPS64 */
/* Logical */
void op_and (void)
@ -552,7 +552,7 @@ void op_clz (void)
RETURN();
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* Those might call libgcc functions. */
@ -743,7 +743,7 @@ void op_dclz (void)
RETURN();
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
#endif /* TARGET_MIPS64 */
/* 64 bits arithmetic */
#if TARGET_LONG_BITS > HOST_LONG_BITS
@ -846,7 +846,7 @@ void op_msubu (void)
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
void op_dmult (void)
{
CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
@ -950,7 +950,7 @@ void op_save_btarget (void)
RETURN();
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
void op_save_btarget64 (void)
{
env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
@ -1784,7 +1784,7 @@ void op_mtc0_entryhi (void)
/* 1k pages not implemented */
val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
val &= env->SEGMask;
#endif
old = env->CP0_EntryHi;
@ -2011,7 +2011,7 @@ void op_mtc0_desave (void)
RETURN();
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
void op_dmfc0_yqmask (void)
{
T0 = env->CP0_YQMask;
@ -2125,7 +2125,7 @@ void op_dmfc0_errorepc (void)
T0 = env->CP0_ErrorEPC;
RETURN();
}
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
#endif /* TARGET_MIPS64 */
/* MIPS MT functions */
void op_mftgpr(void)
@ -3039,7 +3039,7 @@ void op_save_pc (void)
RETURN();
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
void op_save_pc64 (void)
{
env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
@ -3111,7 +3111,7 @@ void op_wsbh(void)
RETURN();
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
void op_dext(void)
{
unsigned int pos = PARAM1;

10
target-mips/op_helper.c
View File

@ -68,7 +68,7 @@ void do_raise_exception_direct (uint32_t exception)
do_raise_exception_direct_err (exception, 0);
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* Those might call libgcc functions. */
void do_dsll (void)
@ -159,7 +159,7 @@ void do_dclz (void)
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
#endif /* TARGET_MIPS64 */
/* 64 bits arithmetic for 32 bits hosts */
#if TARGET_LONG_BITS > HOST_LONG_BITS
@ -228,7 +228,7 @@ void do_div (void)
}
#endif
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
void do_ddiv (void)
{
if (T1 != 0) {
@ -247,7 +247,7 @@ void do_ddivu (void)
}
}
#endif
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
#endif /* TARGET_MIPS64 */
#if defined(CONFIG_USER_ONLY)
void do_mfc0_random (void)
@ -392,7 +392,7 @@ static void r4k_fill_tlb (int idx)
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
tlb = &env->tlb->mmu.r4k.tlb[idx];
tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
tlb->VPN &= env->SEGMask;
#endif
tlb->ASID = env->CP0_EntryHi & 0xFF;

4
target-mips/op_mem.c
View File

@ -190,7 +190,7 @@ void glue(op_sc, MEMSUFFIX) (void)
RETURN();
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
void glue(op_ld, MEMSUFFIX) (void)
{
T0 = glue(ldq, MEMSUFFIX)(T0);
@ -381,7 +381,7 @@ void glue(op_scd, MEMSUFFIX) (void)
}
RETURN();
}
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
#endif /* TARGET_MIPS64 */
void glue(op_lwc1, MEMSUFFIX) (void)
{

2
target-mips/op_template.c
View File

@ -82,7 +82,7 @@ SET_RESET(T2, _T2)
#undef SET_RESET
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
#define SET64(treg, tregname) \
void glue(op_set64, tregname)(void) \
{ \

54
target-mips/translate.c
View File

@ -590,7 +590,7 @@ do { \
} \
} while (0)
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
#define GEN_LOAD_IMM_TN(Tn, Imm) \
do { \
if (Imm == 0) { \
@ -638,7 +638,7 @@ do { \
static always_inline void gen_save_pc(target_ulong pc)
{
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
if (pc == (int32_t)pc) {
gen_op_save_pc(pc);
} else {
@ -651,7 +651,7 @@ static always_inline void gen_save_pc(target_ulong pc)
static always_inline void gen_save_btarget(target_ulong btarget)
{
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
if (btarget == (int32_t)btarget) {
gen_op_save_btarget(btarget);
} else {
@ -802,7 +802,7 @@ static GenOpFunc *gen_op_s##width[] = { \
}
#endif
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
OP_LD_TABLE(d);
OP_LD_TABLE(dl);
OP_LD_TABLE(dr);
@ -852,7 +852,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
switch (opc) {
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_LWU:
op_ldst(lwu);
GEN_STORE_TN_REG(rt, T0);
@ -1048,7 +1048,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
switch (opc) {
case OPC_ADDI:
case OPC_ADDIU:
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DADDI:
case OPC_DADDIU:
#endif
@ -1068,7 +1068,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
case OPC_SLL:
case OPC_SRA:
case OPC_SRL:
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DSLL:
case OPC_DSRA:
case OPC_DSRL:
@ -1091,7 +1091,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
gen_op_add();
opn = "addiu";
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DADDI:
save_cpu_state(ctx, 1);
gen_op_daddo();
@ -1155,7 +1155,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
break;
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DSLL:
gen_op_dsll();
opn = "dsll";
@ -1260,7 +1260,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
gen_op_sub();
opn = "subu";
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DADD:
save_cpu_state(ctx, 1);
gen_op_daddo();
@ -1346,7 +1346,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
break;
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DSLLV:
gen_op_dsllv();
opn = "dsllv";
@ -1451,7 +1451,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
gen_op_multu();
opn = "multu";
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DDIV:
gen_op_ddiv();
opn = "ddiv";
@ -1512,7 +1512,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
gen_op_clz();
opn = "clz";
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DCLO:
gen_op_dclo();
opn = "dclo";
@ -2319,7 +2319,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
case 20:
switch (sel) {
case 0:
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
gen_op_mfc0_xcontext();
rn = "XContext";
@ -2901,7 +2901,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
case 20:
switch (sel) {
case 0:
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
gen_op_mtc0_xcontext();
rn = "XContext";
@ -3111,7 +3111,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
@ -4254,7 +4254,7 @@ die:
#endif
generate_exception(ctx, EXCP_RI);
}
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
#endif /* TARGET_MIPS64 */
static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
int u, int sel, int h)
@ -4604,7 +4604,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
gen_mtc0(env, ctx, rd, ctx->opcode & 0x7);
opn = "mtc0";
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DMFC0:
check_insn(env, ctx, ISA_MIPS3);
if (rt == 0) {
@ -5877,7 +5877,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
/* MIPS16 extension to MIPS32 */
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
/* MDMX extension to MIPS64 */
@ -5987,7 +5987,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
/* MIPS64 specific opcodes */
case OPC_DSLL:
case OPC_DSRL ... OPC_DSRA:
@ -6043,7 +6043,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
}
/* Treat as NOP. */
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DCLZ ... OPC_DCLO:
check_insn(env, ctx, ISA_MIPS64);
check_mips_64(ctx);
@ -6130,7 +6130,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
gen_op_yield();
GEN_STORE_TN_REG(rd, T0);
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
check_insn(env, ctx, ISA_MIPS64R2);
@ -6192,7 +6192,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_MTC0:
case OPC_MFTR:
case OPC_MTTR:
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DMFC0:
case OPC_DMTC0:
#endif
@ -6313,7 +6313,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_CTC1:
gen_cp1(ctx, op1, rt, rd);
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_DMFC1:
case OPC_DMTC1:
check_insn(env, ctx, ISA_MIPS3);
@ -6398,7 +6398,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
case OPC_LWU:
case OPC_LDL ... OPC_LDR:
@ -6665,7 +6665,7 @@ void dump_fpu (CPUState *env)
}
}
#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
/* Debug help: The architecture requires 32bit code to maintain proper
sign-extened values on 64bit machines. */
@ -6720,7 +6720,7 @@ void cpu_dump_state (CPUState *env, FILE *f,
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
if (env->hflags & MIPS_HFLAG_FPU)
fpu_dump_state(env, f, cpu_fprintf, flags);
#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
#endif
}

4
target-mips/translate_init.c
View File

@ -201,7 +201,7 @@ static mips_def_t mips_defs[] =
(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
},
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
{
.name = "R4000",
.CP0_PRid = 0x00000400,
@ -437,7 +437,7 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
env->CP0_SRSCtl = def->CP0_SRSCtl;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
if (def->insn_flags & ISA_MIPS3)
{
env->hflags |= MIPS_HFLAG_64;