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target/mips/tx79: Salvage instructions description comment
This comment describing the tx79 opcodes is helpful. As we will implement these instructions in tx79_translate.c, move the comment there. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-15-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé
parent
e71d0f56ce
commit
d27fadddc6
@ -1130,166 +1130,6 @@ enum {
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};
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/*
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* Overview of the TX79-specific instruction set
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* =============================================
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*
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* The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
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* are only used by the specific quadword (128-bit) LQ/SQ load/store
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* instructions and certain multimedia instructions (MMIs). These MMIs
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* configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
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* or sixteen 8-bit paths.
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*
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* Reference:
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*
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* The Toshiba TX System RISC TX79 Core Architecture manual,
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* https://wiki.qemu.org/File:C790.pdf
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*
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* Three-Operand Multiply and Multiply-Add (4 instructions)
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* --------------------------------------------------------
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* MADD [rd,] rs, rt Multiply/Add
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* MADDU [rd,] rs, rt Multiply/Add Unsigned
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* MULT [rd,] rs, rt Multiply (3-operand)
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* MULTU [rd,] rs, rt Multiply Unsigned (3-operand)
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*
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* Multiply Instructions for Pipeline 1 (10 instructions)
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* ------------------------------------------------------
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* MULT1 [rd,] rs, rt Multiply Pipeline 1
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* MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1
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* DIV1 rs, rt Divide Pipeline 1
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* DIVU1 rs, rt Divide Unsigned Pipeline 1
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* MADD1 [rd,] rs, rt Multiply-Add Pipeline 1
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* MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1
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* MFHI1 rd Move From HI1 Register
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* MFLO1 rd Move From LO1 Register
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* MTHI1 rs Move To HI1 Register
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* MTLO1 rs Move To LO1 Register
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*
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* Arithmetic (19 instructions)
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* ----------------------------
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* PADDB rd, rs, rt Parallel Add Byte
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* PSUBB rd, rs, rt Parallel Subtract Byte
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* PADDH rd, rs, rt Parallel Add Halfword
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* PSUBH rd, rs, rt Parallel Subtract Halfword
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* PADDW rd, rs, rt Parallel Add Word
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* PSUBW rd, rs, rt Parallel Subtract Word
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* PADSBH rd, rs, rt Parallel Add/Subtract Halfword
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* PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte
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* PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte
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* PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword
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* PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword
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* PADDSW rd, rs, rt Parallel Add with Signed Saturation Word
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* PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word
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* PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte
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* PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte
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* PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword
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* PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword
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* PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word
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* PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
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*
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* Min/Max (4 instructions)
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* ------------------------
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* PMAXH rd, rs, rt Parallel Maximum Halfword
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* PMINH rd, rs, rt Parallel Minimum Halfword
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* PMAXW rd, rs, rt Parallel Maximum Word
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* PMINW rd, rs, rt Parallel Minimum Word
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*
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* Absolute (2 instructions)
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* -------------------------
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* PABSH rd, rt Parallel Absolute Halfword
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* PABSW rd, rt Parallel Absolute Word
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*
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* Logical (4 instructions)
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* ------------------------
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* PAND rd, rs, rt Parallel AND
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* POR rd, rs, rt Parallel OR
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* PXOR rd, rs, rt Parallel XOR
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* PNOR rd, rs, rt Parallel NOR
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*
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* Shift (9 instructions)
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* ----------------------
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* PSLLH rd, rt, sa Parallel Shift Left Logical Halfword
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* PSRLH rd, rt, sa Parallel Shift Right Logical Halfword
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* PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword
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* PSLLW rd, rt, sa Parallel Shift Left Logical Word
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* PSRLW rd, rt, sa Parallel Shift Right Logical Word
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* PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word
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* PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word
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* PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word
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* PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word
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*
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* Compare (6 instructions)
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* ------------------------
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* PCGTB rd, rs, rt Parallel Compare for Greater Than Byte
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* PCEQB rd, rs, rt Parallel Compare for Equal Byte
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* PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword
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* PCEQH rd, rs, rt Parallel Compare for Equal Halfword
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* PCGTW rd, rs, rt Parallel Compare for Greater Than Word
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* PCEQW rd, rs, rt Parallel Compare for Equal Word
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*
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* LZC (1 instruction)
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* -------------------
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* PLZCW rd, rs Parallel Leading Zero or One Count Word
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*
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* Quadword Load and Store (2 instructions)
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* ----------------------------------------
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* LQ rt, offset(base) Load Quadword
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* SQ rt, offset(base) Store Quadword
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*
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* Multiply and Divide (19 instructions)
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* -------------------------------------
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* PMULTW rd, rs, rt Parallel Multiply Word
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* PMULTUW rd, rs, rt Parallel Multiply Unsigned Word
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* PDIVW rs, rt Parallel Divide Word
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* PDIVUW rs, rt Parallel Divide Unsigned Word
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* PMADDW rd, rs, rt Parallel Multiply-Add Word
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* PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word
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* PMSUBW rd, rs, rt Parallel Multiply-Subtract Word
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* PMULTH rd, rs, rt Parallel Multiply Halfword
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* PMADDH rd, rs, rt Parallel Multiply-Add Halfword
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* PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword
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* PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword
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* PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword
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* PDIVBW rs, rt Parallel Divide Broadcast Word
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* PMFHI rd Parallel Move From HI Register
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* PMFLO rd Parallel Move From LO Register
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* PMTHI rs Parallel Move To HI Register
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* PMTLO rs Parallel Move To LO Register
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* PMFHL rd Parallel Move From HI/LO Register
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* PMTHL rs Parallel Move To HI/LO Register
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*
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* Pack/Extend (11 instructions)
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* -----------------------------
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* PPAC5 rd, rt Parallel Pack to 5 bits
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* PPACB rd, rs, rt Parallel Pack to Byte
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* PPACH rd, rs, rt Parallel Pack to Halfword
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* PPACW rd, rs, rt Parallel Pack to Word
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* PEXT5 rd, rt Parallel Extend Upper from 5 bits
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* PEXTUB rd, rs, rt Parallel Extend Upper from Byte
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* PEXTLB rd, rs, rt Parallel Extend Lower from Byte
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* PEXTUH rd, rs, rt Parallel Extend Upper from Halfword
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* PEXTLH rd, rs, rt Parallel Extend Lower from Halfword
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* PEXTUW rd, rs, rt Parallel Extend Upper from Word
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* PEXTLW rd, rs, rt Parallel Extend Lower from Word
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*
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* Others (16 instructions)
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* ------------------------
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* PCPYH rd, rt Parallel Copy Halfword
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* PCPYLD rd, rs, rt Parallel Copy Lower Doubleword
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* PCPYUD rd, rs, rt Parallel Copy Upper Doubleword
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* PREVH rd, rt Parallel Reverse Halfword
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* PINTH rd, rs, rt Parallel Interleave Halfword
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* PINTEH rd, rs, rt Parallel Interleave Even Halfword
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* PEXEH rd, rt Parallel Exchange Even Halfword
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* PEXCH rd, rt Parallel Exchange Center Halfword
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* PEXEW rd, rt Parallel Exchange Even Word
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* PEXCW rd, rt Parallel Exchange Center Word
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* QFSRV rd, rs, rt Quadword Funnel Shift Right Variable
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* MFSA rd Move from Shift Amount Register
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* MTSA rs Move to Shift Amount Register
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* MTSAB rs, immediate Move Byte Count to Shift Amount Register
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* MTSAH rs, immediate Move Halfword Count to Shift Amount Register
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* PROT3W rd, rt Parallel Rotate 3 Words
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*
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* MMI (MultiMedia Instruction) encodings
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* ======================================
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*
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@ -14,6 +14,22 @@
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/* Include the auto-generated decoder. */
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#include "decode-tx79.c.inc"
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/*
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* Overview of the TX79-specific instruction set
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* =============================================
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*
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* The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
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* are only used by the specific quadword (128-bit) LQ/SQ load/store
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* instructions and certain multimedia instructions (MMIs). These MMIs
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* configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
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* or sixteen 8-bit paths.
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*
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* Reference:
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*
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* The Toshiba TX System RISC TX79 Core Architecture manual,
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* https://wiki.qemu.org/File:C790.pdf
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*/
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bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
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{
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if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) {
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@ -22,6 +38,30 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
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return false;
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}
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/*
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* Three-Operand Multiply and Multiply-Add (4 instructions)
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* --------------------------------------------------------
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* MADD [rd,] rs, rt Multiply/Add
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* MADDU [rd,] rs, rt Multiply/Add Unsigned
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* MULT [rd,] rs, rt Multiply (3-operand)
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* MULTU [rd,] rs, rt Multiply Unsigned (3-operand)
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*/
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/*
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* Multiply Instructions for Pipeline 1 (10 instructions)
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* ------------------------------------------------------
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* MULT1 [rd,] rs, rt Multiply Pipeline 1
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* MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1
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* DIV1 rs, rt Divide Pipeline 1
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* DIVU1 rs, rt Divide Unsigned Pipeline 1
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* MADD1 [rd,] rs, rt Multiply-Add Pipeline 1
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* MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1
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* MFHI1 rd Move From HI1 Register
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* MFLO1 rd Move From LO1 Register
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* MTHI1 rs Move To HI1 Register
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* MTLO1 rs Move To LO1 Register
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*/
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static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
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{
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gen_store_gpr(cpu_HI[1], a->rd);
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@ -50,6 +90,154 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
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return true;
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}
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/*
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* Arithmetic (19 instructions)
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* ----------------------------
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* PADDB rd, rs, rt Parallel Add Byte
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* PSUBB rd, rs, rt Parallel Subtract Byte
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* PADDH rd, rs, rt Parallel Add Halfword
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* PSUBH rd, rs, rt Parallel Subtract Halfword
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* PADDW rd, rs, rt Parallel Add Word
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* PSUBW rd, rs, rt Parallel Subtract Word
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* PADSBH rd, rs, rt Parallel Add/Subtract Halfword
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* PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte
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* PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte
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* PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword
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* PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword
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* PADDSW rd, rs, rt Parallel Add with Signed Saturation Word
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* PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word
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* PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte
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* PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte
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* PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword
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* PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword
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* PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word
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* PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
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*/
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/*
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* Min/Max (4 instructions)
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* ------------------------
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* PMAXH rd, rs, rt Parallel Maximum Halfword
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* PMINH rd, rs, rt Parallel Minimum Halfword
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* PMAXW rd, rs, rt Parallel Maximum Word
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* PMINW rd, rs, rt Parallel Minimum Word
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*/
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/*
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* Absolute (2 instructions)
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* -------------------------
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* PABSH rd, rt Parallel Absolute Halfword
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* PABSW rd, rt Parallel Absolute Word
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*/
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/*
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* Logical (4 instructions)
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* ------------------------
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* PAND rd, rs, rt Parallel AND
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* POR rd, rs, rt Parallel OR
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* PXOR rd, rs, rt Parallel XOR
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* PNOR rd, rs, rt Parallel NOR
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*/
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/*
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* Shift (9 instructions)
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* ----------------------
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* PSLLH rd, rt, sa Parallel Shift Left Logical Halfword
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* PSRLH rd, rt, sa Parallel Shift Right Logical Halfword
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* PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword
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* PSLLW rd, rt, sa Parallel Shift Left Logical Word
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* PSRLW rd, rt, sa Parallel Shift Right Logical Word
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* PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word
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* PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word
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* PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word
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* PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word
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*/
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/*
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* Compare (6 instructions)
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* ------------------------
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* PCGTB rd, rs, rt Parallel Compare for Greater Than Byte
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* PCEQB rd, rs, rt Parallel Compare for Equal Byte
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* PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword
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* PCEQH rd, rs, rt Parallel Compare for Equal Halfword
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* PCGTW rd, rs, rt Parallel Compare for Greater Than Word
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* PCEQW rd, rs, rt Parallel Compare for Equal Word
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*/
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/*
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* LZC (1 instruction)
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* -------------------
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* PLZCW rd, rs Parallel Leading Zero or One Count Word
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*/
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/*
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* Quadword Load and Store (2 instructions)
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* ----------------------------------------
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* LQ rt, offset(base) Load Quadword
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* SQ rt, offset(base) Store Quadword
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*/
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/*
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* Multiply and Divide (19 instructions)
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* -------------------------------------
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* PMULTW rd, rs, rt Parallel Multiply Word
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* PMULTUW rd, rs, rt Parallel Multiply Unsigned Word
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* PDIVW rs, rt Parallel Divide Word
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* PDIVUW rs, rt Parallel Divide Unsigned Word
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* PMADDW rd, rs, rt Parallel Multiply-Add Word
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* PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word
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* PMSUBW rd, rs, rt Parallel Multiply-Subtract Word
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* PMULTH rd, rs, rt Parallel Multiply Halfword
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* PMADDH rd, rs, rt Parallel Multiply-Add Halfword
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* PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword
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* PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword
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* PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword
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* PDIVBW rs, rt Parallel Divide Broadcast Word
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* PMFHI rd Parallel Move From HI Register
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* PMFLO rd Parallel Move From LO Register
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* PMTHI rs Parallel Move To HI Register
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* PMTLO rs Parallel Move To LO Register
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* PMFHL rd Parallel Move From HI/LO Register
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* PMTHL rs Parallel Move To HI/LO Register
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*/
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/*
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* Pack/Extend (11 instructions)
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* -----------------------------
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* PPAC5 rd, rt Parallel Pack to 5 bits
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* PPACB rd, rs, rt Parallel Pack to Byte
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* PPACH rd, rs, rt Parallel Pack to Halfword
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* PPACW rd, rs, rt Parallel Pack to Word
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* PEXT5 rd, rt Parallel Extend Upper from 5 bits
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* PEXTUB rd, rs, rt Parallel Extend Upper from Byte
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* PEXTLB rd, rs, rt Parallel Extend Lower from Byte
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* PEXTUH rd, rs, rt Parallel Extend Upper from Halfword
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* PEXTLH rd, rs, rt Parallel Extend Lower from Halfword
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* PEXTUW rd, rs, rt Parallel Extend Upper from Word
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* PEXTLW rd, rs, rt Parallel Extend Lower from Word
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*/
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/*
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* Others (16 instructions)
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* ------------------------
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* PCPYH rd, rt Parallel Copy Halfword
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* PCPYLD rd, rs, rt Parallel Copy Lower Doubleword
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* PCPYUD rd, rs, rt Parallel Copy Upper Doubleword
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* PREVH rd, rt Parallel Reverse Halfword
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* PINTH rd, rs, rt Parallel Interleave Halfword
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* PINTEH rd, rs, rt Parallel Interleave Even Halfword
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* PEXEH rd, rt Parallel Exchange Even Halfword
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* PEXCH rd, rt Parallel Exchange Center Halfword
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* PEXEW rd, rt Parallel Exchange Even Word
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* PEXCW rd, rt Parallel Exchange Center Word
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* QFSRV rd, rs, rt Quadword Funnel Shift Right Variable
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* MFSA rd Move from Shift Amount Register
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* MTSA rs Move to Shift Amount Register
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* MTSAB rs, immediate Move Byte Count to Shift Amount Register
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* MTSAH rs, immediate Move Halfword Count to Shift Amount Register
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* PROT3W rd, rt Parallel Rotate 3 Words
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*/
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/* Parallel Copy Halfword */
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static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
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{
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