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target/openrisc: Cache R0 in DisasContext
Finish the race condition fix from the previous patch. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -48,6 +48,9 @@ typedef struct DisasContext {
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/* If not -1, jmp_pc contains this value and so is a direct jump. */
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target_ulong jmp_pc_imm;
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/* The temporary corresponding to register 0 for this compilation. */
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TCGv R0;
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} DisasContext;
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static inline bool is_user(DisasContext *dc)
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@ -64,7 +67,6 @@ static inline bool is_user(DisasContext *dc)
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static TCGv cpu_sr;
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static TCGv cpu_regs[32];
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static TCGv cpu_R0;
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static TCGv cpu_pc;
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static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
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static TCGv cpu_ppc;
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@ -122,7 +124,6 @@ void openrisc_translate_init(void)
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shadow_gpr[0][i]),
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regnames[i]);
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}
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cpu_R0 = cpu_regs[0];
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}
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static void gen_exception(DisasContext *dc, unsigned int excp)
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@ -165,8 +166,12 @@ static void check_ov64s(DisasContext *dc)
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static TCGv cpu_R(DisasContext *dc, int reg)
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{
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if (reg == 0) {
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return dc->R0;
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} else {
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return cpu_regs[reg];
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}
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}
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/*
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* We're about to write to REG. On the off-chance that the user is
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@ -175,7 +180,7 @@ static TCGv cpu_R(DisasContext *dc, int reg)
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static void check_r0_write(DisasContext *dc, int reg)
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{
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if (unlikely(reg == 0)) {
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cpu_regs[0] = cpu_R0;
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dc->R0 = cpu_regs[0];
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}
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}
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@ -747,7 +752,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)
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to cpu_regs[0]. Since l.swa is quite often immediately followed by a
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branch, don't bother reallocating; finish the TB using the "real" R0.
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This also takes care of RB input across the branch. */
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cpu_regs[0] = cpu_R0;
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dc->R0 = cpu_regs[0];
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lab_fail = gen_new_label();
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lab_done = gen_new_label();
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@ -1292,9 +1297,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs)
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/* Allow the TCG optimizer to see that R0 == 0,
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when it's true, which is the common case. */
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if (dc->tb_flags & TB_FLAGS_R0_0) {
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cpu_regs[0] = tcg_const_tl(0);
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dc->R0 = tcg_const_tl(0);
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} else {
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cpu_regs[0] = cpu_R0;
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dc->R0 = cpu_regs[0];
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}
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}
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