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target/riscv: pmu: Rename the counters extension to pmu

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The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.

Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Atish Patra 2022-06-20 16:15:53 -07:00 committed by Alistair Francis
parent a5a92fd6ef
commit d3be1299fb
3 changed files with 5 additions and 5 deletions
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4
target/riscv/cpu.c
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@ -851,7 +851,7 @@ static void riscv_cpu_init(Object *obj)
{ {
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
cpu->cfg.ext_counters = true; cpu->cfg.ext_pmu = true;
cpu->cfg.ext_ifencei = true; cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_icsr = true; cpu->cfg.ext_icsr = true;
cpu->cfg.mmu = true; cpu->cfg.mmu = true;
@ -879,7 +879,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),

2
target/riscv/cpu.h
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@ -397,7 +397,7 @@ struct RISCVCPUConfig {
bool ext_zksed; bool ext_zksed;
bool ext_zksh; bool ext_zksh;
bool ext_zkt; bool ext_zkt;
bool ext_counters; bool ext_pmu;
bool ext_ifencei; bool ext_ifencei;
bool ext_icsr; bool ext_icsr;
bool ext_svinval; bool ext_svinval;

4
target/riscv/csr.c
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@ -74,8 +74,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index; int ctr_index;
if (!cpu->cfg.ext_counters) { if (!cpu->cfg.ext_pmu) {
/* The Counters extensions is not enabled */ /* The PMU extension is not enabled */
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
} }