mirror of
https://github.com/xemu-project/xemu.git
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Merge remote-tracking branch 'remotes/mcayland/qemu-sparc' into staging
* remotes/mcayland/qemu-sparc: sun4m: Add Sun CG3 framebuffer initialisation function sun4m: Add Sun CG3 framebuffer and corresponding OpenBIOS FCode ROM sun4m: fix slavio timer RUN/STOP bit sun4m: Set HostID in NVRAM Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
d47e95c0c8
2
Makefile
2
Makefile
@ -320,7 +320,7 @@ ifdef INSTALL_BLOBS
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||||
BLOBS=bios.bin bios-256k.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
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vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin \
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acpi-dsdt.aml q35-acpi-dsdt.aml \
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ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin \
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ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \
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pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \
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pxe-pcnet.rom pxe-rtl8139.rom pxe-virtio.rom \
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efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \
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@ -10,6 +10,7 @@ CONFIG_EMPTY_SLOT=y
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CONFIG_PCNET_COMMON=y
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CONFIG_LANCE=y
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CONFIG_TCX=y
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CONFIG_CG3=y
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CONFIG_SLAVIO=y
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CONFIG_CS4231=y
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CONFIG_GRLIB=y
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@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP) += omap_lcdc.o
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obj-$(CONFIG_PXA2XX) += pxa2xx_lcd.o
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obj-$(CONFIG_SM501) += sm501.o
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obj-$(CONFIG_TCX) += tcx.o
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obj-$(CONFIG_CG3) += cg3.o
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obj-$(CONFIG_VGA) += vga.o
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385
hw/display/cg3.c
Normal file
385
hw/display/cg3.c
Normal file
@ -0,0 +1,385 @@
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/*
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* QEMU CG3 Frame buffer
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*
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* Copyright (c) 2012 Bob Breuer
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* Copyright (c) 2013 Mark Cave-Ayland
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
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||||
*
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||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
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||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
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*/
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "ui/console.h"
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#include "hw/sysbus.h"
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#include "hw/loader.h"
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/* Change to 1 to enable debugging */
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#define DEBUG_CG3 0
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#define CG3_ROM_FILE "QEMU,cgthree.bin"
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#define FCODE_MAX_ROM_SIZE 0x10000
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#define CG3_REG_SIZE 0x20
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#define CG3_REG_BT458_ADDR 0x0
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#define CG3_REG_BT458_COLMAP 0x4
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#define CG3_REG_FBC_CTRL 0x10
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#define CG3_REG_FBC_STATUS 0x11
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#define CG3_REG_FBC_CURSTART 0x12
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#define CG3_REG_FBC_CUREND 0x13
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#define CG3_REG_FBC_VCTRL 0x14
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/* Control register flags */
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#define CG3_CR_ENABLE_INTS 0x80
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/* Status register flags */
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#define CG3_SR_PENDING_INT 0x80
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#define CG3_SR_1152_900_76_B 0x60
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#define CG3_SR_ID_COLOR 0x01
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#define CG3_VRAM_SIZE 0x100000
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#define CG3_VRAM_OFFSET 0x800000
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#define DPRINTF(fmt, ...) do { \
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if (DEBUG_CG3) { \
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printf("CG3: " fmt , ## __VA_ARGS__); \
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} \
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} while (0);
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#define TYPE_CG3 "cgthree"
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#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
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typedef struct CG3State {
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SysBusDevice parent_obj;
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QemuConsole *con;
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qemu_irq irq;
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hwaddr prom_addr;
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MemoryRegion vram_mem;
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MemoryRegion rom;
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MemoryRegion reg;
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uint32_t vram_size;
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int full_update;
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uint8_t regs[16];
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uint8_t r[256], g[256], b[256];
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uint16_t width, height, depth;
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uint8_t dac_index, dac_state;
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} CG3State;
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static void cg3_update_display(void *opaque)
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{
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CG3State *s = opaque;
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DisplaySurface *surface = qemu_console_surface(s->con);
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const uint8_t *pix;
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uint32_t *data;
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uint32_t dval;
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int x, y, y_start;
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unsigned int width, height;
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ram_addr_t page, page_min, page_max;
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||||
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||||
if (surface_bits_per_pixel(surface) != 32) {
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return;
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}
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width = s->width;
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height = s->height;
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y_start = -1;
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page_min = -1;
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page_max = 0;
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page = 0;
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pix = memory_region_get_ram_ptr(&s->vram_mem);
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data = (uint32_t *)surface_data(surface);
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for (y = 0; y < height; y++) {
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int update = s->full_update;
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page = (y * width) & TARGET_PAGE_MASK;
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update |= memory_region_get_dirty(&s->vram_mem, page, page + width,
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DIRTY_MEMORY_VGA);
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if (update) {
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if (y_start < 0) {
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y_start = y;
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}
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if (page < page_min) {
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page_min = page;
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}
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if (page > page_max) {
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page_max = page;
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}
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for (x = 0; x < width; x++) {
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dval = *pix++;
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dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval];
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*data++ = dval;
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}
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} else {
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if (y_start >= 0) {
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dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
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y_start = -1;
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}
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pix += width;
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data += width;
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}
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}
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s->full_update = 0;
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if (y_start >= 0) {
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dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
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}
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if (page_max >= page_min) {
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memory_region_reset_dirty(&s->vram_mem,
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page_min, page_max - page_min + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA);
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}
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/* vsync interrupt? */
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if (s->regs[0] & CG3_CR_ENABLE_INTS) {
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s->regs[1] |= CG3_SR_PENDING_INT;
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qemu_irq_raise(s->irq);
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}
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}
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static void cg3_invalidate_display(void *opaque)
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{
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CG3State *s = opaque;
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memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);
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}
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static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
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{
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CG3State *s = opaque;
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int val;
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switch (addr) {
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case CG3_REG_BT458_ADDR:
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case CG3_REG_BT458_COLMAP:
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val = 0;
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break;
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case CG3_REG_FBC_CTRL:
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val = s->regs[0];
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break;
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case CG3_REG_FBC_STATUS:
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/* monitor ID 6, board type = 1 (color) */
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val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;
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break;
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case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
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val = s->regs[addr - 0x10];
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"cg3: Unimplemented register read "
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"reg 0x%" HWADDR_PRIx " size 0x%x\n",
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addr, size);
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val = 0;
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break;
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}
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DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);
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return val;
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}
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static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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CG3State *s = opaque;
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uint8_t regval;
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int i;
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DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",
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val, addr, size);
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switch (addr) {
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case CG3_REG_BT458_ADDR:
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s->dac_index = val;
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s->dac_state = 0;
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break;
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case CG3_REG_BT458_COLMAP:
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/* This register can be written to as either a long word or a byte */
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if (size == 1) {
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val <<= 24;
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}
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for (i = 0; i < size; i++) {
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regval = val >> 24;
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switch (s->dac_state) {
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case 0:
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s->r[s->dac_index] = regval;
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s->dac_state++;
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break;
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case 1:
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s->g[s->dac_index] = regval;
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s->dac_state++;
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break;
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case 2:
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s->b[s->dac_index] = regval;
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/* Index autoincrement */
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s->dac_index = (s->dac_index + 1) & 0xff;
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default:
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s->dac_state = 0;
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break;
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}
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val <<= 8;
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}
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s->full_update = 1;
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break;
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case CG3_REG_FBC_CTRL:
|
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s->regs[0] = val;
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break;
|
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case CG3_REG_FBC_STATUS:
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if (s->regs[1] & CG3_SR_PENDING_INT) {
|
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/* clear interrupt */
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s->regs[1] &= ~CG3_SR_PENDING_INT;
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qemu_irq_lower(s->irq);
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}
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break;
|
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case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
|
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s->regs[addr - 0x10] = val;
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break;
|
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default:
|
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qemu_log_mask(LOG_UNIMP,
|
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"cg3: Unimplemented register write "
|
||||
"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
|
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addr, size, val);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static const MemoryRegionOps cg3_reg_ops = {
|
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.read = cg3_reg_read,
|
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.write = cg3_reg_write,
|
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.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 1,
|
||||
.max_access_size = 4,
|
||||
},
|
||||
};
|
||||
|
||||
static const GraphicHwOps cg3_ops = {
|
||||
.invalidate = cg3_invalidate_display,
|
||||
.gfx_update = cg3_update_display,
|
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};
|
||||
|
||||
static void cg3_realizefn(DeviceState *dev, Error **errp)
|
||||
{
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
||||
CG3State *s = CG3(dev);
|
||||
int ret;
|
||||
char *fcode_filename;
|
||||
|
||||
/* FCode ROM */
|
||||
memory_region_init_ram(&s->rom, NULL, "cg3.prom", FCODE_MAX_ROM_SIZE);
|
||||
vmstate_register_ram_global(&s->rom);
|
||||
memory_region_set_readonly(&s->rom, true);
|
||||
sysbus_init_mmio(sbd, &s->rom);
|
||||
|
||||
fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
|
||||
if (fcode_filename) {
|
||||
ret = load_image_targphys(fcode_filename, s->prom_addr,
|
||||
FCODE_MAX_ROM_SIZE);
|
||||
if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
|
||||
error_report("cg3: could not load prom '%s'", CG3_ROM_FILE);
|
||||
}
|
||||
}
|
||||
|
||||
memory_region_init_io(&s->reg, NULL, &cg3_reg_ops, s, "cg3.reg",
|
||||
CG3_REG_SIZE);
|
||||
sysbus_init_mmio(sbd, &s->reg);
|
||||
|
||||
memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size);
|
||||
vmstate_register_ram_global(&s->vram_mem);
|
||||
sysbus_init_mmio(sbd, &s->vram_mem);
|
||||
|
||||
sysbus_init_irq(sbd, &s->irq);
|
||||
|
||||
s->con = graphic_console_init(DEVICE(dev), &cg3_ops, s);
|
||||
qemu_console_resize(s->con, s->width, s->height);
|
||||
}
|
||||
|
||||
static int vmstate_cg3_post_load(void *opaque, int version_id)
|
||||
{
|
||||
CG3State *s = opaque;
|
||||
|
||||
cg3_invalidate_display(s);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_cg3 = {
|
||||
.name = "cg3",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.post_load = vmstate_cg3_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT16(height, CG3State),
|
||||
VMSTATE_UINT16(width, CG3State),
|
||||
VMSTATE_UINT16(depth, CG3State),
|
||||
VMSTATE_BUFFER(r, CG3State),
|
||||
VMSTATE_BUFFER(g, CG3State),
|
||||
VMSTATE_BUFFER(b, CG3State),
|
||||
VMSTATE_UINT8(dac_index, CG3State),
|
||||
VMSTATE_UINT8(dac_state, CG3State),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static void cg3_reset(DeviceState *d)
|
||||
{
|
||||
CG3State *s = CG3(d);
|
||||
|
||||
/* Initialize palette */
|
||||
memset(s->r, 0, 256);
|
||||
memset(s->g, 0, 256);
|
||||
memset(s->b, 0, 256);
|
||||
|
||||
s->dac_state = 0;
|
||||
s->full_update = 1;
|
||||
qemu_irq_lower(s->irq);
|
||||
}
|
||||
|
||||
static Property cg3_properties[] = {
|
||||
DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1),
|
||||
DEFINE_PROP_UINT16("width", CG3State, width, -1),
|
||||
DEFINE_PROP_UINT16("height", CG3State, height, -1),
|
||||
DEFINE_PROP_UINT16("depth", CG3State, depth, -1),
|
||||
DEFINE_PROP_UINT64("prom-addr", CG3State, prom_addr, -1),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void cg3_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->realize = cg3_realizefn;
|
||||
dc->reset = cg3_reset;
|
||||
dc->vmsd = &vmstate_cg3;
|
||||
dc->props = cg3_properties;
|
||||
}
|
||||
|
||||
static const TypeInfo cg3_info = {
|
||||
.name = TYPE_CG3,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(CG3State),
|
||||
.class_init = cg3_class_init,
|
||||
};
|
||||
|
||||
static void cg3_register_types(void)
|
||||
{
|
||||
type_register_static(&cg3_info);
|
||||
}
|
||||
|
||||
type_init(cg3_register_types)
|
||||
@ -22,6 +22,7 @@
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#include "hw/sysbus.h"
|
||||
#include "qemu/error-report.h"
|
||||
#include "qemu/timer.h"
|
||||
#include "hw/sparc/sun4m.h"
|
||||
#include "hw/timer/m48t59.h"
|
||||
@ -561,6 +562,31 @@ static void tcx_init(hwaddr addr, int vram_size, int width,
|
||||
}
|
||||
}
|
||||
|
||||
static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
|
||||
int height, int depth)
|
||||
{
|
||||
DeviceState *dev;
|
||||
SysBusDevice *s;
|
||||
|
||||
dev = qdev_create(NULL, "cgthree");
|
||||
qdev_prop_set_uint32(dev, "vram-size", vram_size);
|
||||
qdev_prop_set_uint16(dev, "width", width);
|
||||
qdev_prop_set_uint16(dev, "height", height);
|
||||
qdev_prop_set_uint16(dev, "depth", depth);
|
||||
qdev_prop_set_uint64(dev, "prom-addr", addr);
|
||||
qdev_init_nofail(dev);
|
||||
s = SYS_BUS_DEVICE(dev);
|
||||
|
||||
/* FCode ROM */
|
||||
sysbus_mmio_map(s, 0, addr);
|
||||
/* DAC */
|
||||
sysbus_mmio_map(s, 1, addr + 0x400000ULL);
|
||||
/* 8-bit plane */
|
||||
sysbus_mmio_map(s, 2, addr + 0x800000ULL);
|
||||
|
||||
sysbus_connect_irq(s, 0, irq);
|
||||
}
|
||||
|
||||
/* NCR89C100/MACIO Internal ID register */
|
||||
|
||||
#define TYPE_MACIO_ID_REGISTER "macio_idreg"
|
||||
@ -914,13 +940,43 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
|
||||
slavio_irq[16], iommu, &ledma_irq, 1);
|
||||
|
||||
if (graphic_depth != 8 && graphic_depth != 24) {
|
||||
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
||||
error_report("Unsupported depth: %d", graphic_depth);
|
||||
exit (1);
|
||||
}
|
||||
num_vsimms = 0;
|
||||
if (num_vsimms == 0) {
|
||||
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
||||
graphic_depth);
|
||||
if (vga_interface_type == VGA_CG3) {
|
||||
if (graphic_depth != 8) {
|
||||
error_report("Unsupported depth: %d", graphic_depth);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if (!(graphic_width == 1024 && graphic_height == 768) &&
|
||||
!(graphic_width == 1152 && graphic_height == 900)) {
|
||||
error_report("Unsupported resolution: %d x %d", graphic_width,
|
||||
graphic_height);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* sbus irq 5 */
|
||||
cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
|
||||
graphic_width, graphic_height, graphic_depth);
|
||||
} else {
|
||||
/* If no display specified, default to TCX */
|
||||
if (graphic_depth != 8 && graphic_depth != 24) {
|
||||
error_report("Unsupported depth: %d", graphic_depth);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if (!(graphic_width == 1024 && graphic_height == 768)) {
|
||||
error_report("Unsupported resolution: %d x %d",
|
||||
graphic_width, graphic_height);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
||||
graphic_depth);
|
||||
}
|
||||
}
|
||||
|
||||
for (i = num_vsimms; i < MAX_VSIMMS; i++) {
|
||||
|
||||
@ -51,7 +51,7 @@ typedef struct CPUTimerState {
|
||||
ptimer_state *timer;
|
||||
uint32_t count, counthigh, reached;
|
||||
/* processor only */
|
||||
uint32_t running;
|
||||
uint32_t run;
|
||||
uint64_t limit;
|
||||
} CPUTimerState;
|
||||
|
||||
@ -177,7 +177,7 @@ static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
|
||||
// only available in processor counter/timer
|
||||
// read start/stop status
|
||||
if (timer_index > 0) {
|
||||
ret = t->running;
|
||||
ret = t->run;
|
||||
} else {
|
||||
ret = 0;
|
||||
}
|
||||
@ -260,16 +260,15 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
|
||||
case TIMER_STATUS:
|
||||
if (slavio_timer_is_user(tc)) {
|
||||
// start/stop user counter
|
||||
if ((val & 1) && !t->running) {
|
||||
if (val & 1) {
|
||||
trace_slavio_timer_mem_writel_status_start(timer_index);
|
||||
ptimer_run(t->timer, 0);
|
||||
t->running = 1;
|
||||
} else if (!(val & 1) && t->running) {
|
||||
} else {
|
||||
trace_slavio_timer_mem_writel_status_stop(timer_index);
|
||||
ptimer_stop(t->timer);
|
||||
t->running = 0;
|
||||
}
|
||||
}
|
||||
t->run = val & 1;
|
||||
break;
|
||||
case TIMER_MODE:
|
||||
if (timer_index == 0) {
|
||||
@ -284,8 +283,9 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
|
||||
if (val & processor) { // counter -> user timer
|
||||
qemu_irq_lower(curr_timer->irq);
|
||||
// counters are always running
|
||||
ptimer_stop(curr_timer->timer);
|
||||
curr_timer->running = 0;
|
||||
if (!curr_timer->run) {
|
||||
ptimer_stop(curr_timer->timer);
|
||||
}
|
||||
// user timer limit is always the same
|
||||
curr_timer->limit = TIMER_MAX_COUNT64;
|
||||
ptimer_set_limit(curr_timer->timer,
|
||||
@ -296,13 +296,8 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
|
||||
s->cputimer_mode |= processor;
|
||||
trace_slavio_timer_mem_writel_mode_user(timer_index);
|
||||
} else { // user timer -> counter
|
||||
// stop the user timer if it is running
|
||||
if (curr_timer->running) {
|
||||
ptimer_stop(curr_timer->timer);
|
||||
}
|
||||
// start the counter
|
||||
ptimer_run(curr_timer->timer, 0);
|
||||
curr_timer->running = 1;
|
||||
// clear this processors user timer bit in config
|
||||
// register
|
||||
s->cputimer_mode &= ~processor;
|
||||
@ -340,7 +335,7 @@ static const VMStateDescription vmstate_timer = {
|
||||
VMSTATE_UINT32(count, CPUTimerState),
|
||||
VMSTATE_UINT32(counthigh, CPUTimerState),
|
||||
VMSTATE_UINT32(reached, CPUTimerState),
|
||||
VMSTATE_UINT32(running, CPUTimerState),
|
||||
VMSTATE_UINT32(run , CPUTimerState),
|
||||
VMSTATE_PTIMER(timer, CPUTimerState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
@ -373,7 +368,7 @@ static void slavio_timer_reset(DeviceState *d)
|
||||
ptimer_set_limit(curr_timer->timer,
|
||||
LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
|
||||
ptimer_run(curr_timer->timer, 0);
|
||||
curr_timer->running = 1;
|
||||
curr_timer->run = 1;
|
||||
}
|
||||
}
|
||||
s->cputimer_mode = 0;
|
||||
|
||||
@ -62,6 +62,8 @@ Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id
|
||||
header->type = 1;
|
||||
header->machine_id = machine_id & 0xff;
|
||||
memcpy(&header->macaddr, macaddr, 6);
|
||||
memcpy(&header->hostid , &macaddr[3], 3);
|
||||
|
||||
/* Calculate checksum */
|
||||
tmp = 0;
|
||||
tmpptr = (uint8_t *)header;
|
||||
|
||||
@ -104,6 +104,7 @@ extern int autostart;
|
||||
|
||||
typedef enum {
|
||||
VGA_NONE, VGA_STD, VGA_CIRRUS, VGA_VMWARE, VGA_XENFB, VGA_QXL,
|
||||
VGA_TCX, VGA_CG3,
|
||||
} VGAInterfaceType;
|
||||
|
||||
extern int vga_interface_type;
|
||||
|
||||
BIN
pc-bios/QEMU,cgthree.bin
Normal file
BIN
pc-bios/QEMU,cgthree.bin
Normal file
Binary file not shown.
@ -11,8 +11,8 @@
|
||||
firmware implementation. The goal is to implement a 100% IEEE
|
||||
1275-1994 (referred to as Open Firmware) compliant firmware.
|
||||
The included images for PowerPC (for 32 and 64 bit PPC CPUs),
|
||||
Sparc32 (including QEMU,tcx.bin) and Sparc64 are built from OpenBIOS SVN
|
||||
revision 1246.
|
||||
Sparc32 (including QEMU,tcx.bin and QEMU,cgthree.bin) and Sparc64 are built
|
||||
from OpenBIOS SVN revision 1246.
|
||||
|
||||
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
|
||||
implementation for certain IBM POWER hardware. The sources are at
|
||||
|
||||
24
vl.c
24
vl.c
@ -2031,6 +2031,16 @@ static bool qxl_vga_available(void)
|
||||
return object_class_by_name("qxl-vga");
|
||||
}
|
||||
|
||||
static bool tcx_vga_available(void)
|
||||
{
|
||||
return object_class_by_name("SUNW,tcx");
|
||||
}
|
||||
|
||||
static bool cg3_vga_available(void)
|
||||
{
|
||||
return object_class_by_name("cgthree");
|
||||
}
|
||||
|
||||
static void select_vgahw (const char *p)
|
||||
{
|
||||
const char *opts;
|
||||
@ -2066,6 +2076,20 @@ static void select_vgahw (const char *p)
|
||||
fprintf(stderr, "Error: QXL VGA not available\n");
|
||||
exit(0);
|
||||
}
|
||||
} else if (strstart(p, "tcx", &opts)) {
|
||||
if (tcx_vga_available()) {
|
||||
vga_interface_type = VGA_TCX;
|
||||
} else {
|
||||
fprintf(stderr, "Error: TCX framebuffer not available\n");
|
||||
exit(0);
|
||||
}
|
||||
} else if (strstart(p, "cg3", &opts)) {
|
||||
if (cg3_vga_available()) {
|
||||
vga_interface_type = VGA_CG3;
|
||||
} else {
|
||||
fprintf(stderr, "Error: CG3 framebuffer not available\n");
|
||||
exit(0);
|
||||
}
|
||||
} else if (!strstart(p, "none", &opts)) {
|
||||
invalid_vga:
|
||||
fprintf(stderr, "Unknown vga type: %s\n", p);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user