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IOAPIC support (initial patch by Filip Navara)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1520 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
1ff5c1a68e
commit
d592d3033d
545
hw/apic.c
545
hw/apic.c
@ -20,6 +20,7 @@
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#include "vl.h"
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//#define DEBUG_APIC
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//#define DEBUG_IOAPIC
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0
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@ -39,6 +40,10 @@
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#define APIC_DM_SIPI 6
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#define APIC_DM_EXTINT 7
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/* APIC destination mode */
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#define APIC_DESTMODE_FLAT 0xf
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#define APIC_DESTMODE_CLUSTER 1
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#define APIC_TRIGGER_EDGE 0
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#define APIC_TRIGGER_LEVEL 1
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@ -49,6 +54,8 @@
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#define APIC_INPUT_POLARITY (1<<13)
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#define APIC_SEND_PENDING (1<<12)
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#define IOAPIC_NUM_PINS 0x18
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#define ESR_ILLEGAL_ADDRESS (1 << 7)
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#define APIC_SV_ENABLE (1 << 8)
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@ -57,8 +64,11 @@ typedef struct APICState {
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CPUState *cpu_env;
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uint32_t apicbase;
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uint8_t id;
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uint8_t arb_id;
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uint8_t tpr;
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uint32_t spurious_vec;
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uint8_t log_dest;
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uint8_t dest_mode;
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uint32_t isr[8]; /* in service register */
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uint32_t tmr[8]; /* trigger mode register */
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uint32_t irr[8]; /* interrupt request register */
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@ -71,9 +81,65 @@ typedef struct APICState {
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uint32_t initial_count;
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int64_t initial_count_load_time, next_time;
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QEMUTimer *timer;
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struct APICState *next_apic;
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} APICState;
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struct IOAPICState {
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uint8_t id;
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uint8_t ioregsel;
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uint32_t irr;
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uint64_t ioredtbl[IOAPIC_NUM_PINS];
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};
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static int apic_io_memory;
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static APICState *first_local_apic = NULL;
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static int last_apic_id = 0;
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static IOAPICState *ioapic_state;
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static void apic_init_ipi(APICState *s);
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
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static void apic_update_irq(APICState *s);
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static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
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uint8_t vector_num, uint8_t polarity,
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uint8_t trigger_mode)
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{
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APICState *apic_iter;
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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case APIC_DM_FIXED:
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/* XXX: arbitration */
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break;
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case APIC_DM_SMI:
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case APIC_DM_NMI:
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break;
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case APIC_DM_INIT:
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/* normal INIT IPI sent to processors */
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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apic_init_ipi(apic_iter);
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}
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return;
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case APIC_DM_EXTINT:
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/* XXX: implement */
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break;
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default:
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return;
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}
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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if (deliver_bitmask & (1 << apic_iter->id))
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apic_set_irq(apic_iter, vector_num, trigger_mode);
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}
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}
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void cpu_set_apic_base(CPUState *env, uint64_t val)
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{
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@ -104,6 +170,7 @@ void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
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{
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APICState *s = env->apic_state;
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s->tpr = (val & 0x0f) << 4;
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apic_update_irq(s);
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}
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uint8_t cpu_get_apic_tpr(CPUX86State *env)
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@ -112,16 +179,24 @@ uint8_t cpu_get_apic_tpr(CPUX86State *env)
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return s->tpr >> 4;
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}
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab)
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int fls_bit(int value)
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{
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int i;
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for(i = 0;i < 8; i++) {
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if (tab[i] != 0) {
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return i * 32 + ffs(tab[i]) - 1;
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}
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}
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return -1;
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unsigned int ret = 0;
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#ifdef HOST_I386
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__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
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return ret;
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#else
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if (value > 0xffff)
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value >>= 16, ret = 16;
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if (value > 0xff)
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value >>= 8, ret += 8;
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if (value > 0xf)
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value >>= 4, ret += 4;
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if (value > 0x3)
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value >>= 2, ret += 2;
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return ret + (value >> 1);
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#endif
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}
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static inline void set_bit(uint32_t *tab, int index)
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@ -140,6 +215,18 @@ static inline void reset_bit(uint32_t *tab, int index)
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tab[i] &= ~mask;
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}
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab)
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{
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int i;
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for(i = 7; i >= 0; i--) {
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if (tab[i] != 0) {
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return i * 32 + fls_bit(tab[i]);
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}
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}
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return -1;
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}
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static int apic_get_ppr(APICState *s)
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{
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int tpr, isrv, ppr;
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@ -156,16 +243,23 @@ static int apic_get_ppr(APICState *s)
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return ppr;
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}
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static int apic_get_arb_pri(APICState *s)
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{
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/* XXX: arbitration */
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return 0;
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}
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/* signal the CPU if an irq is pending */
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static void apic_update_irq(APICState *s)
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{
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int irrv, isrv;
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int irrv, ppr;
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if (!(s->spurious_vec & APIC_SV_ENABLE))
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return;
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irrv = get_highest_priority_int(s->irr);
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if (irrv < 0)
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return;
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isrv = get_highest_priority_int(s->isr);
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/* if the pending irq has less priority, we do not make a new request */
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if (isrv >= 0 && irrv >= isrv)
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ppr = apic_get_ppr(s);
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if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
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return;
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
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}
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@ -187,9 +281,116 @@ static void apic_eoi(APICState *s)
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if (isrv < 0)
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return;
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reset_bit(s->isr, isrv);
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/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
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set the remote IRR bit for level triggered interrupts. */
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apic_update_irq(s);
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}
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static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
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{
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uint32_t mask = 0;
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APICState *apic_iter;
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if (dest_mode == 0) {
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if (dest == 0xff)
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mask = 0xff;
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else
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mask = 1 << dest;
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} else {
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/* XXX: cluster mode */
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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if (dest & apic_iter->log_dest)
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mask |= (1 << apic_iter->id);
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}
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}
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return mask;
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}
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static void apic_init_ipi(APICState *s)
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{
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int i;
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for(i = 0; i < APIC_LVT_NB; i++)
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s->lvt[i] = 1 << 16; /* mask LVT */
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s->tpr = 0;
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s->spurious_vec = 0xff;
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s->log_dest = 0;
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s->dest_mode = 0;
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memset(s->isr, 0, sizeof(s->isr));
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memset(s->tmr, 0, sizeof(s->tmr));
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memset(s->irr, 0, sizeof(s->irr));
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memset(s->lvt, 0, sizeof(s->lvt));
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s->esr = 0;
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memset(s->icr, 0, sizeof(s->icr));
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s->divide_conf = 0;
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s->count_shift = 0;
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s->initial_count = 0;
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s->initial_count_load_time = 0;
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s->next_time = 0;
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}
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static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode, uint8_t vector_num,
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uint8_t polarity, uint8_t trigger_mode)
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{
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uint32_t deliver_bitmask = 0;
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int dest_shorthand = (s->icr[0] >> 18) & 3;
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APICState *apic_iter;
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: serch for focus processor, arbitration */
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dest = s->id;
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case APIC_DM_INIT:
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{
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int trig_mode = (s->icr[0] >> 15) & 1;
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int level = (s->icr[0] >> 14) & 1;
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if (level == 0 && trig_mode == 1) {
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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if (deliver_bitmask & (1 << apic_iter->id)) {
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apic_iter->arb_id = apic_iter->id;
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}
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}
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return;
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}
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}
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break;
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case APIC_DM_SIPI:
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for (apic_iter = first_local_apic; apic_iter != NULL;
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apic_iter = apic_iter->next_apic) {
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if (deliver_bitmask & (1 << apic_iter->id)) {
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/* XXX: SMP support */
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/* apic_startup(apic_iter); */
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}
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}
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return;
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}
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switch (dest_shorthand) {
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case 0:
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deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
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break;
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case 1:
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deliver_bitmask = (1 << s->id);
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break;
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case 2:
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deliver_bitmask = 0xffffffff;
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break;
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case 3:
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deliver_bitmask = 0xffffffff & ~(1 << s->id);
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break;
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}
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
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trigger_mode);
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}
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int apic_get_interrupt(CPUState *env)
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{
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APICState *s = env->apic_state;
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@ -207,6 +408,8 @@ int apic_get_interrupt(CPUState *env)
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if (intno < 0)
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return -1;
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reset_bit(s->irr, intno);
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if (s->tpr && intno <= s->tpr)
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return s->spurious_vec & 0xff;
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set_bit(s->isr, intno);
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apic_update_irq(s);
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return intno;
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@ -220,7 +423,7 @@ static uint32_t apic_get_current_count(APICState *s)
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s->count_shift;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
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/* periodic */
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val = s->initial_count - (d % (s->initial_count + 1));
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val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
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} else {
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if (d >= s->initial_count)
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val = 0;
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@ -238,11 +441,11 @@ static void apic_timer_update(APICState *s, int64_t current_time)
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d = (current_time - s->initial_count_load_time) >>
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s->count_shift;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
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d = ((d / (s->initial_count + 1)) + 1) * (s->initial_count + 1);
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d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
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} else {
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if (d >= s->initial_count)
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goto no_timer;
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d = s->initial_count + 1;
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d = (uint64_t)s->initial_count + 1;
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}
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next_time = s->initial_count_load_time + (d << s->count_shift);
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qemu_mod_timer(s->timer, next_time);
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@ -304,10 +507,19 @@ static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
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case 0x08:
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val = s->tpr;
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break;
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case 0x09:
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val = apic_get_arb_pri(s);
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break;
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case 0x0a:
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/* ppr */
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val = apic_get_ppr(s);
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break;
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case 0x0d:
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val = s->log_dest << 24;
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break;
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case 0x0e:
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val = s->dest_mode << 28;
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break;
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case 0x0f:
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val = s->spurious_vec;
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break;
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@ -372,16 +584,29 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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break;
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case 0x08:
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s->tpr = val;
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apic_update_irq(s);
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break;
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case 0x0b: /* EOI */
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apic_eoi(s);
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break;
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case 0x0d:
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s->log_dest = val >> 24;
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break;
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case 0x0e:
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s->dest_mode = val >> 28;
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break;
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case 0x0f:
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s->spurious_vec = val & 0x1ff;
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apic_update_irq(s);
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break;
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case 0x30:
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s->icr[0] = val;
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apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
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(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
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(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
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break;
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case 0x31:
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s->icr[index & 1] = val;
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s->icr[1] = val;
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break;
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case 0x32 ... 0x37:
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{
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@ -410,7 +635,76 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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}
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}
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static void apic_save(QEMUFile *f, void *opaque)
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{
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APICState *s = opaque;
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int i;
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qemu_put_be32s(f, &s->apicbase);
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qemu_put_8s(f, &s->id);
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qemu_put_8s(f, &s->arb_id);
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qemu_put_8s(f, &s->tpr);
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qemu_put_be32s(f, &s->spurious_vec);
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qemu_put_8s(f, &s->log_dest);
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qemu_put_8s(f, &s->dest_mode);
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for (i = 0; i < 8; i++) {
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qemu_put_be32s(f, &s->isr[i]);
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qemu_put_be32s(f, &s->tmr[i]);
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qemu_put_be32s(f, &s->irr[i]);
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}
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for (i = 0; i < APIC_LVT_NB; i++) {
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qemu_put_be32s(f, &s->lvt[i]);
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}
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qemu_put_be32s(f, &s->esr);
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qemu_put_be32s(f, &s->icr[0]);
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qemu_put_be32s(f, &s->icr[1]);
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qemu_put_be32s(f, &s->divide_conf);
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qemu_put_be32s(f, &s->count_shift);
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qemu_put_be32s(f, &s->initial_count);
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qemu_put_be64s(f, &s->initial_count_load_time);
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qemu_put_be64s(f, &s->next_time);
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}
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static int apic_load(QEMUFile *f, void *opaque, int version_id)
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{
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APICState *s = opaque;
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int i;
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if (version_id != 1)
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return -EINVAL;
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/* XXX: what if the base changes? (registered memory regions) */
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qemu_get_be32s(f, &s->apicbase);
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qemu_get_8s(f, &s->id);
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qemu_get_8s(f, &s->arb_id);
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qemu_get_8s(f, &s->tpr);
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qemu_get_be32s(f, &s->spurious_vec);
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qemu_get_8s(f, &s->log_dest);
|
||||
qemu_get_8s(f, &s->dest_mode);
|
||||
for (i = 0; i < 8; i++) {
|
||||
qemu_get_be32s(f, &s->isr[i]);
|
||||
qemu_get_be32s(f, &s->tmr[i]);
|
||||
qemu_get_be32s(f, &s->irr[i]);
|
||||
}
|
||||
for (i = 0; i < APIC_LVT_NB; i++) {
|
||||
qemu_get_be32s(f, &s->lvt[i]);
|
||||
}
|
||||
qemu_get_be32s(f, &s->esr);
|
||||
qemu_get_be32s(f, &s->icr[0]);
|
||||
qemu_get_be32s(f, &s->icr[1]);
|
||||
qemu_get_be32s(f, &s->divide_conf);
|
||||
qemu_get_be32s(f, &s->count_shift);
|
||||
qemu_get_be32s(f, &s->initial_count);
|
||||
qemu_get_be64s(f, &s->initial_count_load_time);
|
||||
qemu_get_be64s(f, &s->next_time);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void apic_reset(void *opaque)
|
||||
{
|
||||
APICState *s = opaque;
|
||||
apic_init_ipi(s);
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc *apic_mem_read[3] = {
|
||||
apic_mem_readb,
|
||||
@ -427,27 +721,228 @@ static CPUWriteMemoryFunc *apic_mem_write[3] = {
|
||||
int apic_init(CPUState *env)
|
||||
{
|
||||
APICState *s;
|
||||
int i;
|
||||
|
||||
s = malloc(sizeof(APICState));
|
||||
s = qemu_mallocz(sizeof(APICState));
|
||||
if (!s)
|
||||
return -1;
|
||||
memset(s, 0, sizeof(*s));
|
||||
env->apic_state = s;
|
||||
apic_init_ipi(s);
|
||||
s->id = last_apic_id++;
|
||||
s->cpu_env = env;
|
||||
s->apicbase = 0xfee00000 |
|
||||
MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
|
||||
for(i = 0; i < APIC_LVT_NB; i++)
|
||||
s->lvt[i] = 1 << 16; /* mask LVT */
|
||||
s->spurious_vec = 0xff;
|
||||
(s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
|
||||
|
||||
/* XXX: mapping more APICs at the same memory location */
|
||||
if (apic_io_memory == 0) {
|
||||
/* NOTE: the APIC is directly connected to the CPU - it is not
|
||||
on the global memory bus. */
|
||||
apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
|
||||
apic_mem_write, NULL);
|
||||
cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, apic_io_memory);
|
||||
cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
|
||||
apic_io_memory);
|
||||
}
|
||||
s->timer = qemu_new_timer(vm_clock, apic_timer, s);
|
||||
|
||||
register_savevm("apic", 0, 1, apic_save, apic_load, s);
|
||||
qemu_register_reset(apic_reset, s);
|
||||
|
||||
s->next_apic = first_local_apic;
|
||||
first_local_apic = s;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ioapic_service(IOAPICState *s)
|
||||
{
|
||||
uint8_t vector;
|
||||
uint32_t mask;
|
||||
uint64_t entry;
|
||||
uint8_t dest;
|
||||
uint8_t dest_mode;
|
||||
|
||||
for (vector = 0; vector < IOAPIC_NUM_PINS; vector++) {
|
||||
mask = 1 << vector;
|
||||
if (s->irr & mask) {
|
||||
entry = s->ioredtbl[vector];
|
||||
if (!(entry & APIC_LVT_MASKED)) {
|
||||
if (!((entry >> 15) & 1))
|
||||
s->irr &= ~mask;
|
||||
dest = entry >> 56;
|
||||
dest_mode = (entry >> 11) & 1;
|
||||
apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
|
||||
(entry >> 8) & 7, entry & 0xff,
|
||||
(entry >> 13) & 1, (entry >> 15) & 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ioapic_set_irq(void *opaque, int vector, int level)
|
||||
{
|
||||
IOAPICState *s = opaque;
|
||||
|
||||
if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
|
||||
uint32_t mask = 1 << vector;
|
||||
uint64_t entry = s->ioredtbl[vector];
|
||||
|
||||
if ((entry >> 15) & 1) {
|
||||
/* level triggered */
|
||||
if (level) {
|
||||
s->irr |= mask;
|
||||
ioapic_service(s);
|
||||
} else {
|
||||
s->irr &= ~mask;
|
||||
}
|
||||
} else {
|
||||
/* edge triggered */
|
||||
if (level) {
|
||||
s->irr |= mask;
|
||||
ioapic_service(s);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
IOAPICState *s = opaque;
|
||||
int index;
|
||||
uint32_t val = 0;
|
||||
|
||||
addr &= 0xff;
|
||||
if (addr == 0x00) {
|
||||
val = s->ioregsel;
|
||||
} else if (addr == 0x10) {
|
||||
switch (s->ioregsel) {
|
||||
case 0x00:
|
||||
val = s->id << 24;
|
||||
break;
|
||||
case 0x01:
|
||||
val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
|
||||
break;
|
||||
case 0x02:
|
||||
val = 0;
|
||||
break;
|
||||
default:
|
||||
index = (s->ioregsel - 0x10) >> 1;
|
||||
if (index >= 0 && index < IOAPIC_NUM_PINS) {
|
||||
if (s->ioregsel & 1)
|
||||
val = s->ioredtbl[index] >> 32;
|
||||
else
|
||||
val = s->ioredtbl[index] & 0xffffffff;
|
||||
}
|
||||
}
|
||||
#ifdef DEBUG_IOAPIC
|
||||
printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
|
||||
#endif
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
IOAPICState *s = opaque;
|
||||
int index;
|
||||
|
||||
addr &= 0xff;
|
||||
if (addr == 0x00) {
|
||||
s->ioregsel = val;
|
||||
return;
|
||||
} else if (addr == 0x10) {
|
||||
#ifdef DEBUG_IOAPIC
|
||||
printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
|
||||
#endif
|
||||
switch (s->ioregsel) {
|
||||
case 0x00:
|
||||
s->id = (val >> 24) & 0xff;
|
||||
return;
|
||||
case 0x01:
|
||||
case 0x02:
|
||||
return;
|
||||
default:
|
||||
index = (s->ioregsel - 0x10) >> 1;
|
||||
if (index >= 0 && index < IOAPIC_NUM_PINS) {
|
||||
if (s->ioregsel & 1) {
|
||||
s->ioredtbl[index] &= 0xffffffff;
|
||||
s->ioredtbl[index] |= (uint64_t)val << 32;
|
||||
} else {
|
||||
s->ioredtbl[index] &= ~0xffffffffULL;
|
||||
s->ioredtbl[index] |= val;
|
||||
}
|
||||
ioapic_service(s);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void ioapic_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
IOAPICState *s = opaque;
|
||||
int i;
|
||||
|
||||
qemu_put_8s(f, &s->id);
|
||||
qemu_put_8s(f, &s->ioregsel);
|
||||
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
|
||||
qemu_put_be64s(f, &s->ioredtbl[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
IOAPICState *s = opaque;
|
||||
int i;
|
||||
|
||||
if (version_id != 1)
|
||||
return -EINVAL;
|
||||
|
||||
qemu_get_8s(f, &s->id);
|
||||
qemu_get_8s(f, &s->ioregsel);
|
||||
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
|
||||
qemu_get_be64s(f, &s->ioredtbl[i]);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ioapic_reset(void *opaque)
|
||||
{
|
||||
IOAPICState *s = opaque;
|
||||
int i;
|
||||
|
||||
memset(s, 0, sizeof(*s));
|
||||
for(i = 0; i < IOAPIC_NUM_PINS; i++)
|
||||
s->ioredtbl[i] = 1 << 16; /* mask LVT */
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc *ioapic_mem_read[3] = {
|
||||
ioapic_mem_readl,
|
||||
ioapic_mem_readl,
|
||||
ioapic_mem_readl,
|
||||
};
|
||||
|
||||
static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
|
||||
ioapic_mem_writel,
|
||||
ioapic_mem_writel,
|
||||
ioapic_mem_writel,
|
||||
};
|
||||
|
||||
IOAPICState *ioapic_init(void)
|
||||
{
|
||||
IOAPICState *s;
|
||||
int io_memory;
|
||||
|
||||
s = malloc(sizeof(IOAPICState));
|
||||
if (!s)
|
||||
return NULL;
|
||||
ioapic_state = s;
|
||||
ioapic_reset(s);
|
||||
s->id = last_apic_id++;
|
||||
|
||||
io_memory = cpu_register_io_memory(0, ioapic_mem_read,
|
||||
ioapic_mem_write, s);
|
||||
cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
|
||||
|
||||
register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
|
||||
qemu_register_reset(ioapic_reset, s);
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
13
hw/i8259.c
13
hw/i8259.c
@ -55,6 +55,9 @@ struct PicState2 {
|
||||
PicState pics[2];
|
||||
IRQRequestFunc *irq_request;
|
||||
void *irq_request_opaque;
|
||||
/* IOAPIC callback support */
|
||||
SetIRQFunc *alt_irq_func;
|
||||
void *alt_irq_opaque;
|
||||
};
|
||||
|
||||
#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
|
||||
@ -186,6 +189,9 @@ void pic_set_irq_new(void *opaque, int irq, int level)
|
||||
}
|
||||
#endif
|
||||
pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
|
||||
/* used for IOAPIC irqs */
|
||||
if (s->alt_irq_func)
|
||||
s->alt_irq_func(s->alt_irq_opaque, irq, level);
|
||||
pic_update_irq(s);
|
||||
}
|
||||
|
||||
@ -546,3 +552,10 @@ PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
|
||||
s->pics[1].pics_state = s;
|
||||
return s;
|
||||
}
|
||||
|
||||
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
|
||||
void *alt_irq_opaque)
|
||||
{
|
||||
s->alt_irq_func = alt_irq_func;
|
||||
s->alt_irq_opaque = alt_irq_opaque;
|
||||
}
|
||||
|
||||
12
hw/pc.c
12
hw/pc.c
@ -41,6 +41,7 @@ int dummy_refresh_clock;
|
||||
static fdctrl_t *floppy_controller;
|
||||
static RTCState *rtc_state;
|
||||
static PITState *pit;
|
||||
static IOAPICState *ioapic;
|
||||
|
||||
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
|
||||
{
|
||||
@ -70,7 +71,6 @@ int cpu_get_pic_interrupt(CPUState *env)
|
||||
{
|
||||
int intno;
|
||||
|
||||
#ifdef TARGET_X86_64
|
||||
intno = apic_get_interrupt(env);
|
||||
if (intno >= 0) {
|
||||
/* set irq request if a PIC irq is still pending */
|
||||
@ -78,7 +78,6 @@ int cpu_get_pic_interrupt(CPUState *env)
|
||||
pic_update_irq(isa_pic);
|
||||
return intno;
|
||||
}
|
||||
#endif
|
||||
/* read the irq from the PIC */
|
||||
intno = pic_read_irq(isa_pic);
|
||||
return intno;
|
||||
@ -417,7 +416,7 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
|
||||
unsigned long bios_offset, vga_bios_offset;
|
||||
int bios_size, isa_bios_size;
|
||||
PCIBus *pci_bus;
|
||||
|
||||
|
||||
linux_boot = (kernel_filename != NULL);
|
||||
|
||||
/* allocate RAM */
|
||||
@ -557,10 +556,15 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
|
||||
register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
|
||||
register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
|
||||
|
||||
if (pci_enabled)
|
||||
if (pci_enabled) {
|
||||
apic_init(cpu_single_env);
|
||||
ioapic = ioapic_init();
|
||||
}
|
||||
isa_pic = pic_init(pic_irq_request, cpu_single_env);
|
||||
pit = pit_init(0x40, 0);
|
||||
if (pci_enabled) {
|
||||
pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
|
||||
}
|
||||
|
||||
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
|
||||
if (serial_hds[i]) {
|
||||
|
||||
6
vl.h
6
vl.h
@ -695,6 +695,8 @@ extern PicState2 *isa_pic;
|
||||
void pic_set_irq(int irq, int level);
|
||||
void pic_set_irq_new(void *opaque, int irq, int level);
|
||||
PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
|
||||
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
|
||||
void *alt_irq_opaque);
|
||||
int pic_read_irq(PicState2 *s);
|
||||
void pic_update_irq(PicState2 *s);
|
||||
uint32_t pic_intack_read(PicState2 *s);
|
||||
@ -702,8 +704,12 @@ void pic_info(void);
|
||||
void irq_info(void);
|
||||
|
||||
/* APIC */
|
||||
typedef struct IOAPICState IOAPICState;
|
||||
|
||||
int apic_init(CPUState *env);
|
||||
int apic_get_interrupt(CPUState *env);
|
||||
IOAPICState *ioapic_init(void);
|
||||
void ioapic_set_irq(void *opaque, int vector, int level);
|
||||
|
||||
/* i8254.c */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user