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target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v

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This 'shift amount' format is not always 16-bit, so name it
generically as 'sa'. This will help to unify the various
arg_msa decodetree generated structures.

Rename the @bz format -> @bz_v (specific @bz with df=3) and
@bz_df -> @bz (generic @bz).

Since we modify &msa_bz, re-align its arguments, so the other
structures added in the following commits stay visually aligned.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-8-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-19 08:18:25 +02:00
parent 7e9db46d64
commit d61566cf78
2 changed files with 17 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
target/mips/tcg/msa.decode
View File

@ -13,19 +13,18 @@
&r rs rt rd sa
&msa_bz df wt s16
&msa_bz df wt sa
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
BZ_V 010001 01011 ..... ................ @bz
BNZ_V 010001 01111 ..... ................ @bz
BZ_x 010001 110 .. ..... ................ @bz_df
BNZ_x 010001 111 .. ..... ................ @bz_df
BZ_V 010001 01011 ..... ................ @bz_v
BNZ_V 010001 01111 ..... ................ @bz_v
BZ 010001 110 .. ..... ................ @bz
BNZ 010001 111 .. ..... ................ @bz
MSA 011110 --------------------------

20
target/mips/tcg/msa_translate.c
View File

@ -340,7 +340,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
tcg_temp_free_i64(t1);
}
static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
{
TCGv_i64 t0;
@ -358,7 +358,7 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
tcg_gen_trunc_i64_tl(bcond, t0);
tcg_temp_free_i64(t0);
ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
@ -368,15 +368,15 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
{
return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ);
}
static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
{
return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE);
}
static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not)
{
if (!check_msa_enabled(ctx)) {
return true;
@ -389,21 +389,21 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE);
ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
return true;
}
static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a)
{
return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false);
}
static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
{
return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
}
static void gen_msa_i8(DisasContext *ctx)