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Constification
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2916 c046a42c-6fe2-441c-8c8c-71466251a162
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14
sparc-dis.c
14
sparc-dis.c
@ -2206,7 +2206,7 @@ sparc_decode_asi_v8 (int value)
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/* Handle membar masks. */
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static arg membar_table[] =
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static const arg membar_table[] =
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{
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{ 0x40, "#Sync" },
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{ 0x20, "#MemIssue" },
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@ -2238,7 +2238,7 @@ sparc_decode_membar (value)
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/* Handle prefetch args. */
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static arg prefetch_table[] =
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static const arg prefetch_table[] =
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{
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{ 0, "#n_reads" },
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{ 1, "#one_read" },
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@ -2269,7 +2269,7 @@ sparc_decode_prefetch (value)
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/* Handle sparclet coprocessor registers. */
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static arg sparclet_cpreg_table[] =
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static const arg sparclet_cpreg_table[] =
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{
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{ 0, "%ccsr" },
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{ 1, "%ccfr" },
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@ -2320,7 +2320,7 @@ static const struct sparc_opcode **sorted_opcodes;
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/* It is important that we only look at insn code bits as that is how the
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opcode table is hashed. OPCODE_BITS is a table of valid bits for each
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of the main types (0,1,2,3). */
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static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
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static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
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#define HASH_INSN(INSN) \
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((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
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struct opcode_hash {
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@ -2340,7 +2340,7 @@ static int compute_arch_mask PARAMS ((unsigned long));
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((((int)(value)) << ((8 * sizeof (int)) - bits)) \
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>> ((8 * sizeof (int)) - bits) )
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static char *reg_names[] =
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static const char * const reg_names[] =
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{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
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"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
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@ -2361,7 +2361,7 @@ static char *reg_names[] =
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/* These are ordered according to there register number in
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rdpr and wrpr insns. */
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static char *v9_priv_reg_names[] =
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static const char * const v9_priv_reg_names[] =
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{
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"tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
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"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
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@ -2371,7 +2371,7 @@ static char *v9_priv_reg_names[] =
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/* These are ordered according to there register number in
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rd and wr insns (-16). */
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static char *v9a_asr_reg_names[] =
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static const char * const v9a_asr_reg_names[] =
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{
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"pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
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"softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
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