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tcg/ppc: Support vector multiply
For Altivec, this is always an expansion. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Richard Henderson
parent
dabae0971b
commit
d9897efa1f
@ -162,7 +162,7 @@ extern bool have_altivec;
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#define TCG_TARGET_HAS_shs_vec 0
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#define TCG_TARGET_HAS_shv_vec 1
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#define TCG_TARGET_HAS_cmp_vec 1
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#define TCG_TARGET_HAS_mul_vec 0
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 0
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@ -523,6 +523,25 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define VSRAB VX4(772)
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#define VSRAH VX4(836)
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#define VSRAW VX4(900)
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#define VRLB VX4(4)
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#define VRLH VX4(68)
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#define VRLW VX4(132)
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#define VMULEUB VX4(520)
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#define VMULEUH VX4(584)
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#define VMULOUB VX4(8)
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#define VMULOUH VX4(72)
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#define VMSUMUHM VX4(38)
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#define VMRGHB VX4(12)
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#define VMRGHH VX4(76)
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#define VMRGHW VX4(140)
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#define VMRGLB VX4(268)
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#define VMRGLH VX4(332)
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#define VMRGLW VX4(396)
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#define VPKUHUM VX4(14)
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#define VPKUWUM VX4(78)
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#define VAND VX4(1028)
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#define VANDC VX4(1092)
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@ -2875,6 +2894,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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case INDEX_op_sarv_vec:
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return vece <= MO_32;
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case INDEX_op_cmp_vec:
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case INDEX_op_mul_vec:
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case INDEX_op_shli_vec:
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case INDEX_op_shri_vec:
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case INDEX_op_sari_vec:
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@ -2987,7 +3007,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 },
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shlv_op[4] = { VSLB, VSLH, VSLW, 0 },
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shrv_op[4] = { VSRB, VSRH, VSRW, 0 },
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sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 };
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sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 },
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mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
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mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
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muleu_op[4] = { VMULEUB, VMULEUH, 0, 0 },
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mulou_op[4] = { VMULOUB, VMULOUH, 0, 0 },
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pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
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rotl_op[4] = { VRLB, VRLH, VRLW, 0 };
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TCGType type = vecl + TCG_TYPE_V64;
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TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
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@ -3076,6 +3102,29 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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}
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break;
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case INDEX_op_ppc_mrgh_vec:
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insn = mrgh_op[vece];
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break;
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case INDEX_op_ppc_mrgl_vec:
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insn = mrgl_op[vece];
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break;
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case INDEX_op_ppc_muleu_vec:
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insn = muleu_op[vece];
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break;
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case INDEX_op_ppc_mulou_vec:
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insn = mulou_op[vece];
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break;
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case INDEX_op_ppc_pkum_vec:
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insn = pkum_op[vece];
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break;
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case INDEX_op_ppc_rotl_vec:
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insn = rotl_op[vece];
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break;
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case INDEX_op_ppc_msum_vec:
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tcg_debug_assert(vece == MO_16);
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tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
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return;
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case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
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case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
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case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
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@ -3145,6 +3194,53 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
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}
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}
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static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
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TCGv_vec v1, TCGv_vec v2)
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{
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TCGv_vec t1 = tcg_temp_new_vec(type);
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TCGv_vec t2 = tcg_temp_new_vec(type);
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TCGv_vec t3, t4;
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switch (vece) {
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case MO_8:
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case MO_16:
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vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
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tcgv_vec_arg(v1), tcgv_vec_arg(v2));
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vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
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tcgv_vec_arg(v1), tcgv_vec_arg(v2));
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vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0),
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tcgv_vec_arg(t1), tcgv_vec_arg(t2));
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vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1),
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tcgv_vec_arg(t1), tcgv_vec_arg(t2));
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vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0),
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tcgv_vec_arg(v0), tcgv_vec_arg(t1));
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break;
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case MO_32:
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t3 = tcg_temp_new_vec(type);
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t4 = tcg_temp_new_vec(type);
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tcg_gen_dupi_vec(MO_8, t4, -16);
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vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1),
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tcgv_vec_arg(v2), tcgv_vec_arg(t4));
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vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
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tcgv_vec_arg(v1), tcgv_vec_arg(v2));
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tcg_gen_dupi_vec(MO_8, t3, 0);
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vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3),
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tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3));
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vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3),
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tcgv_vec_arg(t3), tcgv_vec_arg(t4));
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tcg_gen_add_vec(MO_32, v0, t2, t3);
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tcg_temp_free_vec(t3);
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tcg_temp_free_vec(t4);
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break;
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default:
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g_assert_not_reached();
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}
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tcg_temp_free_vec(t1);
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tcg_temp_free_vec(t2);
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}
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void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
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TCGArg a0, ...)
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{
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@ -3171,6 +3267,10 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
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v2 = temp_tcgv_vec(arg_temp(a2));
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expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
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break;
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case INDEX_op_mul_vec:
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v2 = temp_tcgv_vec(arg_temp(a2));
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expand_vec_mul(type, vece, v0, v1, v2);
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break;
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default:
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g_assert_not_reached();
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}
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@ -3217,6 +3317,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
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static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
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static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
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static const TCGTargetOpDef v_v_v_v
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= { .args_ct_str = { "v", "v", "v", "v" } };
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switch (op) {
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case INDEX_op_goto_ptr:
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@ -3354,6 +3456,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_add_vec:
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case INDEX_op_sub_vec:
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case INDEX_op_mul_vec:
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case INDEX_op_and_vec:
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case INDEX_op_or_vec:
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case INDEX_op_xor_vec:
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@ -3371,6 +3474,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_shlv_vec:
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case INDEX_op_shrv_vec:
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case INDEX_op_sarv_vec:
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case INDEX_op_ppc_mrgh_vec:
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case INDEX_op_ppc_mrgl_vec:
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case INDEX_op_ppc_muleu_vec:
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case INDEX_op_ppc_mulou_vec:
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case INDEX_op_ppc_pkum_vec:
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case INDEX_op_ppc_rotl_vec:
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return &v_v_v;
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case INDEX_op_not_vec:
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case INDEX_op_dup_vec:
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@ -3379,6 +3488,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_st_vec:
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case INDEX_op_dupm_vec:
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return &v_r;
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case INDEX_op_ppc_msum_vec:
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return &v_v_v_v;
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default:
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return NULL;
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@ -3,3 +3,11 @@
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* emitted by tcg_expand_vec_op. For those familiar with GCC internals,
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* consider these to be UNSPEC with names.
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*/
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DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC)
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DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC)
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