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piix: fix 32bit pci hole
Make the 32bit pci hole start at end of ram, so all possible address space is covered. We used to try and make addresses aligned so they are easier to cover with MTRRs, but since they are cosmetic on KVM, this is probably not worth worrying about. Of course the firmware can use less than that. Leaving space unused is no problem, mapping pci bars outside the hole causes problems though. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -170,6 +170,7 @@ static void pc_init1(QEMUMachineInitArgs *args,
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if (pci_enabled) {
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pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,
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system_memory, system_io, args->ram_size,
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below_4g_mem_size,
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above_4g_mem_size,
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pci_memory, ram_memory);
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} else {
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@ -311,6 +311,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io,
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ram_addr_t ram_size,
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ram_addr_t below_4g_mem_size,
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ram_addr_t above_4g_mem_size,
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MemoryRegion *pci_address_space,
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MemoryRegion *ram_memory)
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@ -340,15 +341,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
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f->ram_memory = ram_memory;
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i440fx = I440FX_PCI_HOST_BRIDGE(dev);
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/* Set PCI window size the way seabios has always done it. */
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/* Power of 2 so bios can cover it with a single MTRR */
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if (ram_size <= 0x80000000) {
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i440fx->pci_info.w32.begin = 0x80000000;
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} else if (ram_size <= 0xc0000000) {
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i440fx->pci_info.w32.begin = 0xc0000000;
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} else {
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i440fx->pci_info.w32.begin = 0xe0000000;
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}
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i440fx->pci_info.w32.begin = below_4g_mem_size;
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/* setup pci memory mapping */
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pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
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@ -182,6 +182,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io,
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ram_addr_t ram_size,
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ram_addr_t below_4g_mem_size,
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ram_addr_t above_4g_mem_size,
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MemoryRegion *pci_memory,
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MemoryRegion *ram_memory);
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