xemu-project/xemu
1
0
Fork 0
mirror of https://github.com/xemu-project/xemu.git synced 2024-11-25 12:40:08 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

target/ppc: Pass integer to helper_mtvscr

Browse Source 
We can re-use this helper elsewhere if we're not passing
in an entire vector register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20190215100058.20015-10-mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson 2019-02-15 10:00:50 +00:00 committed by David Gibson
parent 03dce230db
commit dedfaac74e
3 changed files with 17 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/ppc/helper.h
View File

@ -294,7 +294,7 @@ DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr)
DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
DEF_HELPER_2(mtvscr, void, env, avr)
DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_3(lvebx, void, env, avr, tl)
DEF_HELPER_3(lvehx, void, env, avr, tl)
DEF_HELPER_3(lvewx, void, env, avr, tl)

6
target/ppc/int_helper.c
View File

@ -457,10 +457,10 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh)
}
}
void helper_mtvscr(CPUPPCState *env, ppc_avr_t *r)
void helper_mtvscr(CPUPPCState *env, uint32_t vscr)
{
env->vscr = r->VsrW(3);
set_flush_to_zero(vscr_nj, &env->vec_status);
env->vscr = vscr;
set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
}
void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)

17
target/ppc/translate/vmx-impl.inc.c
View File

@ -196,14 +196,23 @@ static void gen_mfvscr(DisasContext *ctx)
static void gen_mtvscr(DisasContext *ctx)
{
TCGv_ptr p;
TCGv_i32 val;
int bofs;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
p = gen_avr_ptr(rB(ctx->opcode));
gen_helper_mtvscr(cpu_env, p);
tcg_temp_free_ptr(p);
val = tcg_temp_new_i32();
bofs = avr64_offset(rB(ctx->opcode), true);
#ifdef HOST_WORDS_BIGENDIAN
bofs += 3 * 4;
#endif
tcg_gen_ld_i32(val, cpu_env, bofs);
gen_helper_mtvscr(cpu_env, val);
tcg_temp_free_i32(val);
}
#define GEN_VX_VMUL10(name, add_cin, ret_carry) \