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target/hppa: Rearrange log conditions
We will be fixing do_cond vs signed overflow, which requires that do_log_cond not rely on do_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -432,6 +432,15 @@ static DisasCond cond_make_f(void)
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};
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}
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static DisasCond cond_make_t(void)
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{
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return (DisasCond){
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.c = TCG_COND_ALWAYS,
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.a0 = NULL,
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.a1 = NULL,
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};
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}
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static DisasCond cond_make_n(void)
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{
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return (DisasCond){
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@ -930,17 +939,50 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res,
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return cond;
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}
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/* Similar, but for logicals, where the carry and overflow bits are not
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computed, and use of them is undefined. */
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/*
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* Similar, but for logicals, where the carry and overflow bits are not
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* computed, and use of them is undefined.
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*
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* Undefined or not, hardware does not trap. It seems reasonable to
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* assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's
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* how cases c={2,3} are treated.
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*/
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static DisasCond do_log_cond(unsigned cf, TCGv_reg res)
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{
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switch (cf >> 1) {
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case 4: case 5: case 6:
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cf &= 1;
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break;
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switch (cf) {
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case 0: /* never */
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case 9: /* undef, C */
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case 11: /* undef, C & !Z */
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case 12: /* undef, V */
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return cond_make_f();
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case 1: /* true */
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case 8: /* undef, !C */
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case 10: /* undef, !C | Z */
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case 13: /* undef, !V */
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return cond_make_t();
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case 2: /* == */
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return cond_make_0(TCG_COND_EQ, res);
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case 3: /* <> */
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return cond_make_0(TCG_COND_NE, res);
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case 4: /* < */
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return cond_make_0(TCG_COND_LT, res);
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case 5: /* >= */
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return cond_make_0(TCG_COND_GE, res);
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case 6: /* <= */
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return cond_make_0(TCG_COND_LE, res);
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case 7: /* > */
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return cond_make_0(TCG_COND_GT, res);
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case 14: /* OD */
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case 15: /* EV */
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return do_cond(cf, res, NULL, NULL);
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default:
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g_assert_not_reached();
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}
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return do_cond(cf, res, res, res);
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}
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/* Similar, but for shift/extract/deposit conditions. */
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