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tcg: Add CONFIG_ATOMIC64
Allow qemu to build on 32-bit hosts without 64-bit atomic ops. Even if we only allow 32-bit hosts to multi-thread emulate 32-bit guests, we still need some way to handle the 32-bit guest using a 64-bit atomic operation. Do so by dropping back to single-step. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
7ebee43ee3
commit
df79b996a7
33
configure
vendored
33
configure
vendored
@ -4544,6 +4544,35 @@ EOF
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fi
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fi
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#########################################
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# See if 64-bit atomic operations are supported.
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# Note that without __atomic builtins, we can only
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# assume atomic loads/stores max at pointer size.
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cat > $TMPC << EOF
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#include <stdint.h>
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int main(void)
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{
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uint64_t x = 0, y = 0;
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#ifdef __ATOMIC_RELAXED
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y = __atomic_load_8(&x, 0);
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__atomic_store_8(&x, y, 0);
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__atomic_compare_exchange_8(&x, &y, x, 0, 0, 0);
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__atomic_exchange_8(&x, y, 0);
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__atomic_fetch_add_8(&x, y, 0);
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#else
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typedef char is_host64[sizeof(void *) >= sizeof(uint64_t) ? 1 : -1];
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__sync_lock_test_and_set(&x, y);
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__sync_val_compare_and_swap(&x, y, 0);
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__sync_fetch_and_add(&x, y);
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#endif
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return 0;
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}
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EOF
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if compile_prog "" "" ; then
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atomic64=yes
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fi
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########################################
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# check if getauxval is available.
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@ -5510,6 +5539,10 @@ if test "$atomic128" = "yes" ; then
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echo "CONFIG_ATOMIC128=y" >> $config_host_mak
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fi
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if test "$atomic64" = "yes" ; then
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echo "CONFIG_ATOMIC64=y" >> $config_host_mak
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fi
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if test "$getauxval" = "yes" ; then
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echo "CONFIG_GETAUXVAL=y" >> $config_host_mak
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fi
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4
cputlb.c
4
cputlb.c
@ -687,8 +687,10 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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#define DATA_SIZE 4
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#include "atomic_template.h"
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#ifdef CONFIG_ATOMIC64
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#define DATA_SIZE 8
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#include "atomic_template.h"
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#endif
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#ifdef CONFIG_ATOMIC128
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#define DATA_SIZE 16
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@ -713,8 +715,10 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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#define DATA_SIZE 4
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#include "atomic_template.h"
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#ifdef CONFIG_ATOMIC64
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#define DATA_SIZE 8
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#include "atomic_template.h"
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#endif
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/* Code access functions. */
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@ -101,6 +101,11 @@ int64_t HELPER(mulsh_i64)(int64_t arg1, int64_t arg2)
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return h;
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}
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void HELPER(exit_atomic)(CPUArchState *env)
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{
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cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC());
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}
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#ifndef CONFIG_SOFTMMU
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/* The softmmu versions of these helpers are in cputlb.c. */
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@ -130,8 +135,10 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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#define DATA_SIZE 4
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#include "atomic_template.h"
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#ifdef CONFIG_ATOMIC64
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#define DATA_SIZE 8
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#include "atomic_template.h"
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#endif
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/* The following is only callable from other helpers, and matches up
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with the softmmu version. */
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22
tcg/tcg-op.c
22
tcg/tcg-op.c
@ -2040,14 +2040,20 @@ typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32);
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typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64);
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#endif
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#ifdef CONFIG_ATOMIC64
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# define WITH_ATOMIC64(X) X,
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#else
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# define WITH_ATOMIC64(X)
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#endif
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static void * const table_cmpxchg[16] = {
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[MO_8] = gen_helper_atomic_cmpxchgb,
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[MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,
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[MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,
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[MO_32 | MO_LE] = gen_helper_atomic_cmpxchgl_le,
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[MO_32 | MO_BE] = gen_helper_atomic_cmpxchgl_be,
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[MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le,
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[MO_64 | MO_BE] = gen_helper_atomic_cmpxchgq_be,
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WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le)
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WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_cmpxchgq_be)
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};
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void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
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@ -2117,6 +2123,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
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}
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tcg_temp_free_i64(t1);
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} else if ((memop & MO_SIZE) == MO_64) {
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#ifdef CONFIG_ATOMIC64
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gen_atomic_cx_i64 gen;
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gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
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@ -2131,6 +2138,9 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
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#else
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gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv);
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#endif
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#else
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gen_helper_exit_atomic(tcg_ctx.tcg_env);
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#endif /* CONFIG_ATOMIC64 */
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} else {
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TCGv_i32 c32 = tcg_temp_new_i32();
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TCGv_i32 n32 = tcg_temp_new_i32();
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@ -2218,6 +2228,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
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memop = tcg_canonicalize_memop(memop, 1, 0);
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if ((memop & MO_SIZE) == MO_64) {
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#ifdef CONFIG_ATOMIC64
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gen_atomic_op_i64 gen;
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gen = table[memop & (MO_SIZE | MO_BSWAP)];
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@ -2232,6 +2243,9 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
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#else
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gen(ret, tcg_ctx.tcg_env, addr, val);
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#endif
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#else
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gen_helper_exit_atomic(tcg_ctx.tcg_env);
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#endif /* CONFIG_ATOMIC64 */
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} else {
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TCGv_i32 v32 = tcg_temp_new_i32();
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TCGv_i32 r32 = tcg_temp_new_i32();
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@ -2256,8 +2270,8 @@ static void * const table_##NAME[16] = { \
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[MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \
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[MO_32 | MO_LE] = gen_helper_atomic_##NAME##l_le, \
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[MO_32 | MO_BE] = gen_helper_atomic_##NAME##l_be, \
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[MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le, \
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[MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be, \
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WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le) \
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WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be) \
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}; \
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void tcg_gen_atomic_##NAME##_i32 \
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(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \
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@ -15,23 +15,28 @@ DEF_HELPER_FLAGS_2(sar_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
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DEF_HELPER_FLAGS_2(mulsh_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
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DEF_HELPER_FLAGS_2(muluh_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env)
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#ifdef CONFIG_SOFTMMU
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DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG,
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i32, env, tl, i32, i32, i32)
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DEF_HELPER_FLAGS_5(atomic_cmpxchgw_be, TCG_CALL_NO_WG,
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i32, env, tl, i32, i32, i32)
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DEF_HELPER_FLAGS_5(atomic_cmpxchgl_be, TCG_CALL_NO_WG,
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i32, env, tl, i32, i32, i32)
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DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG,
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i64, env, tl, i64, i64, i32)
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DEF_HELPER_FLAGS_5(atomic_cmpxchgw_le, TCG_CALL_NO_WG,
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i32, env, tl, i32, i32, i32)
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DEF_HELPER_FLAGS_5(atomic_cmpxchgl_be, TCG_CALL_NO_WG,
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i32, env, tl, i32, i32, i32)
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DEF_HELPER_FLAGS_5(atomic_cmpxchgl_le, TCG_CALL_NO_WG,
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i32, env, tl, i32, i32, i32)
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#ifdef CONFIG_ATOMIC64
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DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG,
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i64, env, tl, i64, i64, i32)
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DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG,
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i64, env, tl, i64, i64, i32)
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#endif
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#ifdef CONFIG_ATOMIC64
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#define GEN_ATOMIC_HELPERS(NAME) \
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DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \
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TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
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@ -47,17 +52,33 @@ DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG,
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TCG_CALL_NO_WG, i64, env, tl, i64, i32) \
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DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_be), \
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TCG_CALL_NO_WG, i64, env, tl, i64, i32)
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#else
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#define GEN_ATOMIC_HELPERS(NAME) \
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DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \
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TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
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DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \
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TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
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DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \
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TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
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DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \
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TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
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DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \
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TCG_CALL_NO_WG, i32, env, tl, i32, i32)
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#endif /* CONFIG_ATOMIC64 */
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#else
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DEF_HELPER_FLAGS_4(atomic_cmpxchgb, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
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DEF_HELPER_FLAGS_4(atomic_cmpxchgw_be, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
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DEF_HELPER_FLAGS_4(atomic_cmpxchgl_be, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
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DEF_HELPER_FLAGS_4(atomic_cmpxchgq_be, TCG_CALL_NO_WG, i64, env, tl, i64, i64)
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DEF_HELPER_FLAGS_4(atomic_cmpxchgw_le, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
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DEF_HELPER_FLAGS_4(atomic_cmpxchgl_be, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
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DEF_HELPER_FLAGS_4(atomic_cmpxchgl_le, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
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#ifdef CONFIG_ATOMIC64
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DEF_HELPER_FLAGS_4(atomic_cmpxchgq_be, TCG_CALL_NO_WG, i64, env, tl, i64, i64)
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DEF_HELPER_FLAGS_4(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64)
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#endif
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#ifdef CONFIG_ATOMIC64
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#define GEN_ATOMIC_HELPERS(NAME) \
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DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), \
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TCG_CALL_NO_WG, i32, env, tl, i32) \
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@ -73,6 +94,19 @@ DEF_HELPER_FLAGS_4(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64)
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TCG_CALL_NO_WG, i64, env, tl, i64) \
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DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_be), \
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TCG_CALL_NO_WG, i64, env, tl, i64)
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#else
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#define GEN_ATOMIC_HELPERS(NAME) \
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DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), \
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TCG_CALL_NO_WG, i32, env, tl, i32) \
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DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), \
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TCG_CALL_NO_WG, i32, env, tl, i32) \
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DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), \
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TCG_CALL_NO_WG, i32, env, tl, i32) \
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DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), \
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TCG_CALL_NO_WG, i32, env, tl, i32) \
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DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), \
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TCG_CALL_NO_WG, i32, env, tl, i32)
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#endif /* CONFIG_ATOMIC64 */
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#endif /* CONFIG_SOFTMMU */
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15
tcg/tcg.h
15
tcg/tcg.h
@ -1204,14 +1204,23 @@ TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \
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(CPUArchState *env, target_ulong addr, TYPE val, \
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TCGMemOpIdx oi, uintptr_t retaddr);
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#ifdef CONFIG_ATOMIC64
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#define GEN_ATOMIC_HELPER_ALL(NAME) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
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GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
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GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
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GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
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#else
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#define GEN_ATOMIC_HELPER_ALL(NAME) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
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#endif
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GEN_ATOMIC_HELPER_ALL(fetch_add)
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GEN_ATOMIC_HELPER_ALL(fetch_sub)
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