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vga: bugfixes for cirrus and virtio-gpu

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Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20170213-1' into staging

vga: bugfixes for cirrus and virtio-gpu

# gpg: Signature made Mon 13 Feb 2017 08:14:47 GMT
# gpg:                using RSA key 0x4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/pull-vga-20170213-1:
  Revert "cirrus: allow zero source pitch in pattern fill rops"
  cirrus: fix patterncopy checks
  cirrus: replace debug printf with trace points
  vga: replace debug printf with trace points
  virtio-gpu: fix resource leak in virgl_cmd_resource_unref
  virtio-gpu: fix memory leak in set scanout

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2017-02-13 10:54:49 +00:00
commit df96bfab49
5 changed files with 67 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
hw/display/cirrus_vga.c
View File

@ -28,6 +28,7 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "trace.h"
#include "hw/hw.h"
#include "hw/pci/pci.h"
#include "ui/console.h"
@ -272,6 +273,9 @@ static void cirrus_update_memory_access(CirrusVGAState *s);
static bool blit_region_is_unsafe(struct CirrusVGAState *s,
int32_t pitch, int32_t addr)
{
if (!pitch) {
return true;
}
if (pitch < 0) {
int64_t min = addr
+ ((int64_t)s->cirrus_blt_height - 1) * pitch
@ -290,11 +294,8 @@ static bool blit_region_is_unsafe(struct CirrusVGAState *s,
return false;
}
static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only,
bool zero_src_pitch_ok)
static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only)
{
int32_t check_pitch;
/* should be the case, see cirrus_bitblt_start */
assert(s->cirrus_blt_width > 0);
assert(s->cirrus_blt_height > 0);
@ -303,10 +304,6 @@ static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only,
return true;
}
if (!s->cirrus_blt_dstpitch) {
return true;
}
if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
s->cirrus_blt_dstaddr)) {
return true;
@ -314,13 +311,7 @@ static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only,
if (dst_only) {
return false;
}
check_pitch = s->cirrus_blt_srcpitch;
if (!zero_src_pitch_ok && !check_pitch) {
check_pitch = s->cirrus_blt_width;
}
if (blit_region_is_unsafe(s, check_pitch,
if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch,
s->cirrus_blt_srcaddr)) {
return true;
}
@ -683,14 +674,39 @@ static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
}
}
static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
const uint8_t * src)
static int cirrus_bitblt_common_patterncopy(CirrusVGAState *s, bool videosrc)
{
uint32_t patternsize;
uint8_t *dst;
uint8_t *src;
dst = s->vga.vram_ptr + s->cirrus_blt_dstaddr;
if (blit_is_unsafe(s, false, true)) {
if (videosrc) {
switch (s->vga.get_bpp(&s->vga)) {
case 8:
patternsize = 64;
break;
case 15:
case 16:
patternsize = 128;
break;
case 24:
case 32:
default:
patternsize = 256;
break;
}
s->cirrus_blt_srcaddr &= ~(patternsize - 1);
if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) {
return 0;
}
src = s->vga.vram_ptr + s->cirrus_blt_srcaddr;
} else {
src = s->cirrus_bltbuf;
}
if (blit_is_unsafe(s, true)) {
return 0;
}
@ -709,7 +725,7 @@ static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
{
cirrus_fill_t rop_func;
if (blit_is_unsafe(s, true, true)) {
if (blit_is_unsafe(s, true)) {
return 0;
}
rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
@ -731,8 +747,7 @@ static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
{
return cirrus_bitblt_common_patterncopy(s, s->vga.vram_ptr +
(s->cirrus_blt_srcaddr & ~7));
return cirrus_bitblt_common_patterncopy(s, true);
}
static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
@ -810,7 +825,7 @@ static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
{
if (blit_is_unsafe(s, false, false))
if (blit_is_unsafe(s, false))
return 0;
return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
@ -831,7 +846,7 @@ static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
if (s->cirrus_srccounter > 0) {
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
cirrus_bitblt_common_patterncopy(s, false);
the_end:
s->cirrus_srccounter = 0;
cirrus_bitblt_reset(s);
@ -1852,12 +1867,14 @@ static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
break;
}
trace_vga_cirrus_write_blt(address, value);
return (uint8_t) value;
}
static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
uint8_t value)
{
trace_vga_cirrus_write_blt(address, value);
switch (address) {
case (CIRRUS_MMIO_BLTBGCOLOR + 0):
cirrus_vga_write_gr(s, 0x00, value);
@ -2607,9 +2624,7 @@ static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
break;
}
}
#if defined(DEBUG_VGA)
printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
#endif
trace_vga_cirrus_read_io(addr, val);
return val;
}
@ -2626,9 +2641,7 @@ static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
if (vga_ioport_invalid(s, addr)) {
return;
}
#ifdef DEBUG_VGA
printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
#endif
trace_vga_cirrus_write_io(addr, val);
switch (addr) {
case 0x3c0:

12
hw/display/trace-events
View File

@ -119,3 +119,15 @@ qxl_set_client_capabilities_unsupported_by_revision(int qid, int revision) "%d r
qxl_render_blit(int32_t stride, int32_t left, int32_t right, int32_t top, int32_t bottom) "stride=%d [%d, %d, %d, %d]"
qxl_render_guest_primary_resized(int32_t width, int32_t height, int32_t stride, int32_t bytes_pp, int32_t bits_pp) "%dx%d, stride %d, bpp %d, depth %d"
qxl_render_update_area_done(void *cookie) "%p"
# hw/display/vga.c
vga_std_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
vga_std_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
vga_vbe_read(uint32_t index, uint32_t val) "index 0x%x, val 0x%x"
vga_vbe_write(uint32_t index, uint32_t val) "index 0x%x, val 0x%x"
# hw/display/cirrus_vga.c
vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"

27
hw/display/vga.c
View File

@ -34,12 +34,9 @@
#include "hw/xen/xen.h"
#include "trace.h"
//#define DEBUG_VGA
//#define DEBUG_VGA_MEM
//#define DEBUG_VGA_REG
//#define DEBUG_BOCHS_VBE
/* 16 state changes per vertical frame @60 Hz */
#define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
@ -428,9 +425,7 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr)
break;
}
}
#if defined(DEBUG_VGA)
printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
#endif
trace_vga_std_read_io(addr, val);
return val;
}
@ -443,9 +438,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
if (vga_ioport_invalid(s, addr)) {
return;
}
#ifdef DEBUG_VGA
printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
#endif
trace_vga_std_write_io(addr, val);
switch(addr) {
case VGA_ATT_W:
@ -733,9 +726,7 @@ uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
} else {
val = 0;
}
#ifdef DEBUG_BOCHS_VBE
printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
#endif
trace_vga_vbe_read(s->vbe_index, val);
return val;
}
@ -750,9 +741,7 @@ void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
VGACommonState *s = opaque;
if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
#ifdef DEBUG_BOCHS_VBE
printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
#endif
trace_vga_vbe_write(s->vbe_index, val);
switch(s->vbe_index) {
case VBE_DISPI_INDEX_ID:
if (val == VBE_DISPI_ID0 ||
@ -1543,17 +1532,9 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
height, format, s->line_offset,
s->vram_ptr + (s->start_addr * 4));
dpy_gfx_replace_surface(s->con, surface);
#ifdef DEBUG_VGA
printf("VGA: Using shared surface for depth=%d swap=%d\n",
depth, byteswap);
#endif
} else {
qemu_console_resize(s->con, disp_width, height);
surface = qemu_console_surface(s->con);
#ifdef DEBUG_VGA
printf("VGA: Using shadow surface for depth=%d swap=%d\n",
depth, byteswap);
#endif
}
s->last_scr_width = disp_width;
s->last_scr_height = height;

8
hw/display/virtio-gpu-3d.c
View File

@ -77,10 +77,18 @@ static void virgl_cmd_resource_unref(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
struct virtio_gpu_resource_unref unref;
struct iovec *res_iovs = NULL;
int num_iovs = 0;
VIRTIO_GPU_FILL_CMD(unref);
trace_virtio_gpu_cmd_res_unref(unref.resource_id);
virgl_renderer_resource_detach_iov(unref.resource_id,
&res_iovs,
&num_iovs);
if (res_iovs != NULL && num_iovs != 0) {
virtio_gpu_cleanup_mapping_iov(res_iovs, num_iovs);
}
virgl_renderer_resource_unref(unref.resource_id);
}

1
hw/display/virtio-gpu.c
View File

@ -608,6 +608,7 @@ static void virtio_gpu_set_scanout(VirtIOGPU *g,
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
return;
}
pixman_image_unref(rect);
dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, scanout->ds);
}