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target/arm: Use tcg_constant for do_coproc_insn

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-26 09:30:22 -07:00 committed by Peter Maydell
parent f5fd5f64b4
commit dfbbf5e1f9
1 changed files with 13 additions and 30 deletions
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43
target/arm/translate.c
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@ -4689,8 +4689,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
* Note that on XScale all cp0..c13 registers do an access check * Note that on XScale all cp0..c13 registers do an access check
* call in order to handle c15_cpar. * call in order to handle c15_cpar.
*/ */
TCGv_ptr tmpptr;
TCGv_i32 tcg_syn, tcg_isread;
uint32_t syndrome; uint32_t syndrome;
/* Note that since we are an implementation which takes an /* Note that since we are an implementation which takes an
@ -4733,14 +4731,10 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_set_pc_im(s, s->pc_curr);
tmpptr = tcg_const_ptr(ri); gen_helper_access_check_cp_reg(cpu_env,
tcg_syn = tcg_const_i32(syndrome); tcg_constant_ptr(ri),
tcg_isread = tcg_const_i32(isread); tcg_constant_i32(syndrome),
gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_constant_i32(isread));
tcg_isread);
tcg_temp_free_ptr(tmpptr);
tcg_temp_free_i32(tcg_syn);
tcg_temp_free_i32(tcg_isread);
} else if (ri->type & ARM_CP_RAISES_EXC) { } else if (ri->type & ARM_CP_RAISES_EXC) {
/* /*
* The readfn or writefn might raise an exception; * The readfn or writefn might raise an exception;
@ -4776,13 +4770,11 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
TCGv_i64 tmp64; TCGv_i64 tmp64;
TCGv_i32 tmp; TCGv_i32 tmp;
if (ri->type & ARM_CP_CONST) { if (ri->type & ARM_CP_CONST) {
tmp64 = tcg_const_i64(ri->resetvalue); tmp64 = tcg_constant_i64(ri->resetvalue);
} else if (ri->readfn) { } else if (ri->readfn) {
TCGv_ptr tmpptr;
tmp64 = tcg_temp_new_i64(); tmp64 = tcg_temp_new_i64();
tmpptr = tcg_const_ptr(ri); gen_helper_get_cp_reg64(tmp64, cpu_env,
gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr); tcg_constant_ptr(ri));
tcg_temp_free_ptr(tmpptr);
} else { } else {
tmp64 = tcg_temp_new_i64(); tmp64 = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset); tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
@ -4797,13 +4789,10 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
} else { } else {
TCGv_i32 tmp; TCGv_i32 tmp;
if (ri->type & ARM_CP_CONST) { if (ri->type & ARM_CP_CONST) {
tmp = tcg_const_i32(ri->resetvalue); tmp = tcg_constant_i32(ri->resetvalue);
} else if (ri->readfn) { } else if (ri->readfn) {
TCGv_ptr tmpptr;
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
tmpptr = tcg_const_ptr(ri); gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
tcg_temp_free_ptr(tmpptr);
} else { } else {
tmp = load_cpu_offset(ri->fieldoffset); tmp = load_cpu_offset(ri->fieldoffset);
} }
@ -4833,24 +4822,18 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
tcg_temp_free_i32(tmplo); tcg_temp_free_i32(tmplo);
tcg_temp_free_i32(tmphi); tcg_temp_free_i32(tmphi);
if (ri->writefn) { if (ri->writefn) {
TCGv_ptr tmpptr = tcg_const_ptr(ri); gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri),
gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64); tmp64);
tcg_temp_free_ptr(tmpptr);
} else { } else {
tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset); tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
} }
tcg_temp_free_i64(tmp64); tcg_temp_free_i64(tmp64);
} else { } else {
TCGv_i32 tmp = load_reg(s, rt);
if (ri->writefn) { if (ri->writefn) {
TCGv_i32 tmp; gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
TCGv_ptr tmpptr;
tmp = load_reg(s, rt);
tmpptr = tcg_const_ptr(ri);
gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
tcg_temp_free_ptr(tmpptr);
tcg_temp_free_i32(tmp); tcg_temp_free_i32(tmp);
} else { } else {
TCGv_i32 tmp = load_reg(s, rt);
store_cpu_offset(tmp, ri->fieldoffset, 4); store_cpu_offset(tmp, ri->fieldoffset, 4);
} }
} }